RM0004 Datasheet, PDF (283/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

Storage architecture
RM0004
5.2.1
Unless specifically noted, the discussion of coherency in this section applies to the core
complex data cache only. The instruction cache is not snooped for general coherency with
other caches; however, it is snooped when the Instruction Cache Block Invalidate (icbi)
instruction is executed by this processor or any processor in the system.
Memory/Cache access attributes
Some memory characteristics can be set on a page basis by using the WIMGE bits in the
translation lookaside buffer (TLB) entries. These bits allow both uniprocessor and
multiprocessor system designs to exploit numerous system-level performance
optimizations. The WIMGE attributes control the following:
● Write-through (W bit)
● Caching-inhibited (I bit)
● Memory-coherency-required (M bit)
● Guarded (G bit)
● Endianness (E bit)
In addition to the WIMGE bits, the Book E MMU model defines the following attributes on a
page basis:
● User-definable (U0, U1, U2, U3)
The EIS defines the following optional attributes, which are manipulated by software through
MMU assist register 2 (MAS2):
● Alternate coherency mode (ACM). The ACM attribute, programmed through
MAS2[ACM], allows an implementation to employ multiple coherency methods and to
participate in multiple coherency protocols. If the M attribute (memory coherence
required) is not set for a page (M = 0), the page has no coherency associated with it
and the ACM attribute is ignored. If the M attribute is set for a page (M = 1), the ACM
attribute determines the coherency domain (or protocol) used. ACM values are
implementation dependent.
● Variable length encoding (VLE). The VLE attribute, MAS2[VLE], identifies pages that
contain instructions from the VLE instruction set. If VLE = 0, instructions fetched from
the page are decoded and executed as PowerPC (and associated EIS APUs)
instructions. If VLE = 1, instructions fetched from the page are decoded and executed
as Power Embedded instructions.
Consult the user documentation to determine whether the EIS-defined attributes are
implemented.
The WIMGE attributes are programmed by the operating system for each page. The W and
I attributes control how the processor performing an access uses its own cache. The M
attribute ensures that coherency is maintained for all copies of the addressed memory
location. The G attribute prevents speculative loading from the addressed memory location.
(An operation is said to be performed speculatively if, at the time that it is performed, it is not
known to be required by the sequential execution model.) The E attribute defines the order
in which the bytes that comprise a multiple-byte data object are stored in memory (big- or
little-endian).
The WIMGE attributes occupy 5 bits in the TLB entries for page address translation. The
operating system writes the WIMGE bits for each page into the TLB entries in system
memory as it maps translations. For more information, see TLB entries on page 319.”
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