RM0004 Datasheet, PDF (815/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

Instruction set
RM0004
tlbsx
TLB Search indexed
tlbsx
rA,rB
Book E Supervisor
tlbsx
0
56
10 11
15 16
20 21
30 31
011111
///⁽¹⁾
rA
rB
1 1 1 0 0 1 0 0 1 0 /¹
1. This field is defined as allocated by the Book E architecture, for possible use in an implementation. These bits are not
implemented by the EIS.
if RA!=0 then generate exception
EA = ³²0 || GPR(RB)_32:63
ProcessID = MAS6(SPID)
AS = MAS6(SAS)
VA0 = AS || ^{(MMUCFG[PIDSIZE] + 1)}0 || EA
VA1 = AS || ProcessID || EA
if Valid_TLB_matching_entry_exists (VA0) or Valid_TLB_matching_entry_exists
(VA1)
#
#
MAS0, MAS1, MAS2, MAS3 = result
EA calculation:
Addressing ModeEA for rA=0EA for rA≠0
32_{0 || rB32:63}32_{0 || (rA+rB)32:63}
Note that rA = 0 is a preferred form for tlbsx and that some ST implementations take an
illegal instruction exception program interrupt if rA != 0.
Virtual address 0 (VA0) is the value AS || ^{(MMUCFG[PIDSIZE] + 1)}0 || EA
Virtual address 1 (VA1) is the value AS || ProcessID || EA
If the TLB contains an entry corresponding to VA, an implementation-dependent value is
placed into an implementation-dependent-specified target. Otherwise the contents of the
implementation-dependent-specified target are left undefined.
Other registers altered: implementation-dependent. See Supervisor-level tlb management
instructions on page 183.
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