RM0004 Datasheet, PDF (262/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

RM0004
Interrupts and exceptions
4.7.4
Table 155. Data Storage Interrupt Register Settings
Register
Setting
SRR0
SRR1
ESR
MSR
DEAR
Set to the effective address of the instruction causing the interrupt
Set to the MSR contents at the time of the interrupt
FPSet if the instruction causing the interrupt is a floating-point load or store; otherwise
cleared
STSet if the instruction causing the interrupt is a store or store-class cache management
instruction; otherwise cleared
DLKDLK is set when a DSI occurs because dcbtls, dcbtstls, or dcblc is executed in user
mode and MSR[UCLE] = 0.
APSet if the instruction causing the interrupt is an auxiliary processor load or store;
otherwise cleared
BOSet if the instruction caused a byte-ordering exception; otherwise cleared
All other defined ESR bits are cleared.
CE, ME, and DE are unchanged. All other MSR bits are cleared.
Set to the effective address of a byte that lies both within the range of bytes being
accessed by the access or cache management instruction and within the page whose
access caused the exception
Instruction execution resumes at address IVPR[32–47] || IVOR2[48–59] || 0b0000.
Instruction storage interrupt
An instruction storage interrupt occurs when no higher priority exception exists and an
instruction storage exception is presented to the interrupt mechanism. Instruction storage
exception conditions are described in Table 156.
Table 156. Instruction storage interrupt exception conditions
Exception
Cause
Execute access
control exception
In user mode, an instruction fetch attempts to access a memory location that is
not user mode execute enabled (page access control bit UX = 0).
In supervisor mode, an instruction fetch attempts to access a memory location
that is not supervisor mode execute enabled (page access control bit SX = 0).
Byte-ordering
exception
The implementation cannot fetch the instruction in the byte order specified by the
page’s endian attribute. The EIS defines that accesses that cross a page
boundary such that endianness changes cause a byte-ordering exception.
Note that Book E provides this exception to assist implementations that cannot dynamically
switch byte ordering between consecutive accesses, do not support the byte order for a
class of accesses, or do not support misaligned accesses using a specific byte order.
When an instruction storage interrupt occurs, the processor suppresses execution of the
instruction causing the exception.
SRR0, SRR1, MSR, and ESR are updated as shown in Table 157.
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