RM0004 Datasheet, PDF (269/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

Interrupts and exceptions
RM0004
Note:
4.7.13
Note:
4.7.14
Table 167. Fixed-interval timer interrupt register settings
Register
Setting
SRR0
SRR1
MSR
TSR
Set to the effective address of the next instruction to be executed.
Set to the MSR contents at the time of the interrupt.
CE, ME, and DE are unchanged. All other MSR bits are cleared.
FIS is set.
Instruction execution resumes at address IVPR[32–47] || IVOR11[48–59] || 0b0000.
To avoid redundant fixed-interval timer interrupts, before reenabling MSR[EE], the interrupt
handling routine must clear TSR[FIS] by writing a word to TSR using mtspr with a 1 in any
bit position to be cleared and 0 in all others. The data written to the TSR is not direct data,
but a mask. Writing a 1 causes the bit to be cleared; writing a 0 has no effect.
Watchdog timer interrupt
A watchdog timer interrupt occurs when no higher priority exception exists, a watchdog
timer exception exists (TSR[WIS] = 1), and the interrupt is enabled (TCR[WIE] = 1 and
MSR[CE] = 1).
MSR[CE] also enables the critical input interrupt.
CSRR0, CSRR1, MSR, and TSR are updated as shown in Table 168.
Table 168. Watchdog timer interrupt register settings
Register
Setting
CSRR0 Set to the effective address of the next instruction to be executed.
CSRR1 Set to the MSR contents at the time of the interrupt.
MSR
TSR
ME is unchanged; all other MSR bits are cleared.
WIS is set.
Instruction execution resumes at address IVPR[32–47] || IVOR12[48–59] || 0b0000.
To avoid redundant watchdog timer interrupts, before reenabling MSR[CE], the interrupt
handling routine must clear TSR[WIS] by writing a word to TSR using mtspr with a 1 in any
bit position to be cleared and 0 in all others. The data written to the TSR is not direct data,
but a mask. Writing a 1 to this bit causes it to be cleared; writing a 0 has no effect.
Data tlb error interrupt
A data TLB error interrupt occurs when no higher priority exception exists and the exception
described in Table 169 is presented to the interrupt mechanism.
Table 169. Data tlb error interrupt exception conditions
Exception
Description
Data TLB miss exception Virtual addresses associated with an instruction fetch do not match any
valid TLB entry.
269/1176