RM0004 Datasheet, PDF (837/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

Auxiliary processing units (APUs)
RM0004
Signal processing embedded floating-point status and control register (SPEFSCR)
The embedded floating-point APUs use the SPEFSCR, which is described in
Chapter 2.14.1: Signal processing, embedded floating-point status, control register
(SPEFSCR) on page 119.” The SPE APU also uses SPEFSCR. Status and control bits are
shared for vector floating-point operations, single-precision floating-point operations and
SPE vector operations. The SPEFSCR is implemented as SPR number 512 and is read and
written by mfspr and mtspr in both user and supervisor mode. Vector floating-point
instructions affect both the high- and low-element floating-point status flags (bits 34–39 and
50–55). Scalar SPFP instructions affect only the low-element flags and leave the high
element flags undefined.
Embedded floating-point exception bit—ESR[SPE]
ESR[SPE] is defined as the embedded floating-point exception bit. This bit is set whenever
the processor takes an interrupt related to the execution of the embedded floating-point
instructions. (Note that the same bit is used for SPE APU exceptions. Thus, SPE and
embedded floating-point interrupts are indistinguishable in the ESR.)
Embedded floating-point interrupts
The following sections describe the embedded floating-point APU interrupts:
● SPE/embedded floating-point unavailable interrupt on page 837”
● Embedded floating-point data interrupt on page 837”
● Embedded floating-point round interrupt on page 838”
SPE/embedded floating-point unavailable interrupt
The SPE/embedded floating-point unavailable interrupt vector is used by the embedded
scalar double-precision floating-point APU and the embedded vector single-precision
floating-point APU. It is not used by the embedded scalar single-precision floating-point
APU. The SPE/embedded floating-point unavailable interrupt occurs when an embedded
vector floating-point or an embedded scalar double-precision floating-point instruction is
executed and bit 38 of the MSR is not set. If the SPE/embedded floating-point unavailable
interrupt occurs, the processor suppresses execution of the instruction causing the
exception.
The SRR0, SRR1, MSR, and ESR registers are modified as follows:
● SRR0 is set to the EA of the instruction causing the interrupt.
● SRR1 is set to the contents of the MSR at the time of the interrupt.
● MSR bits CE, ME, and DE are unchanged. All other bits are cleared.
● ESR[24] is set. All other ESR bits are cleared.
Instruction execution resumes at address IVPR[0–47]||IVOR32[48–59]||0b0000.
This interrupt is also used by the SPE APU in the same manner. It should be used by
software to determine if the application is using the upper 32 bits of the GPRs and thus is
required to save and restore them on a context switch.
Embedded floating-point data interrupt
The embedded floating-point data interrupt vector is used for enabled floating-point invalid
operation/input error, underflow, overflow, and divide-by-zero exceptions (collectively called
floating-point data exceptions). When one of these enabled exceptions occurs, the
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