M36DR432A Datasheet, PDF (7/46 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36DR432A, M36DR432B
FLASH MEMORY COMPONENT
Organization
The Flash Chip is organized as 2Mb x16 bits. A0-
A20 are the address lines, DQ0-DQ15 are the
Data Input/Output. Memory control is provided by
Chip Enable EF, Output Enable GF and Write En-
able WF inputs.
Reset RPF is used to reset all the memory circuitry
and to set the chip in power down mode if this
function is enabled by a proper setting of the Con-
figuration Register. Erase and Program operations
are controlled by an internal Program/Erase Con-
troller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, DQ6 and DQ2
provide Toggle signals and DQ5 provides error bit
to indicate the state of the P/E.C operations.
Memory Blocks
The device features asymmetrically blocked archi-
tecture. The Flash Chip has an array of 71 blocks
and is divided into two banks A and B, providing
Dual Bank operations. While programming or
erasing in Bank A, read operations are possible
into Bank B or vice versa. The memory also fea-
tures an erase suspend allowing to read or pro-
gram in another block within the same bank. Once
suspended the erase can be resumed. The Bank
Size and Sectorization are summarized in Table 4.
Parameter Blocks are located at the top of the
memory address space for the Top version, and at
the bottom for the Bottom version. The memory
maps are shown in Tables 5, 6, 7 and 8.
The Program and Erase operations are managed
automatically by the P/E.C. Block protection
against Program or Erase provides additional data
security. All blocks are protected at Power Up. In-
structions are provided to protect or unprotect any
block in the application. A second register locks
the protection status while WPF is low (see Block
Locking description). The Reset command does
not affect the configuration of unprotected blocks
and the Configuration Register status.
Device Operations
The following operations can be performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write command, Output Dis-
able, Standby, Reset/Power Down and Block
Locking. See Table 9.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Status or the Configuration Register
status. Read operation of the memory array is per-
formed in asynchronous page mode, that provides
fast access time. Data is internally read and stored
in a page buffer. The page has a size of 4 words
and is addressed by A0-A1 address inputs. Read
operations of the Electronic Signature, the Status
Register, the CFI, the Block Protection Status, the
Configuration Register status and the Security
Code are performed as single asynchronous read
cycles (Random Read). Both Chip Enable EF and
Output Enable GF must be at V_IL in order to read
the output of the memory.
Write. Write operations are used to give Instruc-
tion Commands to the memory or to latch Input
Data to be programmed. A write operation is initi-
ated when Chip Enable EF and Write Enable WF
are at V_IL with Output Enable GF at V_IH. Address-
es are latched on the falling edge of WF or EF
whichever occurs last. Commands and Input Data
are latched on the rising edge of WF or EF which-
ever occurs first. Noise pulses of less than 5ns typ-
ical on EF, WF and GF signals do not start a write
cycle.
Dual Bank Operations. The Dual Bank allows to
read data from one bank of memory while a pro-
gram or erase operation is in progress in the other
bank of the memory. Read and Write cycles can
be initiated for simultaneous operations in different
banks without any delay. Status Register during
Program or Erase must be monitored using an ad-
dress within the bank being modified.
Output Disable. The data outputs are high im-
pedance when the Output Enable GF is at V_IH with
Write Enable WF at V_IH.
Standby. The memory is in standby when Chip
Enable EF is at V_IH and the P/E.C. is idle. The
power consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable GF or Write Enable WF in-
puts.
Automatic Standby. When in Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
ters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while out-
puts still drive the bus.
Power Down. The memory is in Power Down
when the Configuration Register is set for Power
Down and RPF is at V_IL. The power consumption
is reduced to the Power Down level, and Outputs
are in high impedance, independent of the Chip
Enable EF, Output Enable GF or Write Enable WF
inputs.
Block Locking. Any combination of blocks can
be temporarily protected against Program or
Erase by setting the lock register and pulling WPF
to V_IL (see Block Lock instruction).
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