M36DR432A Datasheet, PDF (12/46 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36DR432A, M36DR432B
The bank address is don’t care for this instruction.
The Electronic Signature can be read from the
memory allowing programming equipment or ap-
plications to automatically match their interface to
the characteristics of Flash Chip. The Manufactur-
er Code is output when the address lines A0 and
A1 are at V_IL, the Device Code is output when A0
is at V_IH with A1 at V_IL.
The codes are output on DQ0-DQ7 with DQ8-
DQ15 at 00h. The AS instruction also allows the
access to the Block Protection Status. After giving
the AS instruction, A0 is set to V_IL with A1 at V_IH,
while A12-A20 define the address of the block to
be verified. A read in these conditions will output a
01h if the block is protected and a 00h if the block
is not protected.
The AS Instruction finally allows the access to the
Configuration Register status if both A0 and A1
are set to V_IH. If DQ10 is '0' only the Reset function
is active as RPF is set to V_IL (default at power-up).
If DQ10 is '1' both the Reset and the Power Down
functions will be achieved by pulling RPF to V_IL.
The other bits of the Configuration Register are re-
served and must be ignored. A reset command
puts the device in read array mode.
Write Configuration Register (CR) Instruc-
tion. This instruction uses two Coded Cycles fol-
lowed by one write cycle giving the command 60h
to address 555h. A further write cycle giving the
command 03h writes the contents of address bits
A0-A15 to the 16 bits configuration register. Bits
written by inputs A0-A9 and A11-A15 are reserved
for future use. Address input A10 defines the sta-
tus of the Reset/Power Down functions. It must be
set to V_IL to enable only the Reset function and to
V_IH to enable also the Power Down function. At
Power Up all the Configuration Register bits are
reset to '0'.
Enter Bypass Mode (EBY) Instruction. This in-
struction uses the two Coded cycles followed by
one write cycle giving the command 20h to ad-
dress 555h for mode set-up. Once in Bypass
mode, the device will accept the Exit Bypass
(XBY) and Program or Double Word Program in
Bypass mode (PGBY, DPGBY) commands. The
Bypass mode allows to reduce the overall pro-
gramming time when large memory arrays need to
be programmed.
Exit Bypass Mode (XBY) Instruction. This in-
struction uses two write cycles. The first inputs to
the memory the command 90h and the second in-
puts the Exit Bypass mode confirm (00h). After the
XBY instruction, the device resets to Read Memo-
ry Array mode.
Program in Bypass Mode (PGBY) Instruc-
tion. This instruction uses two write cycles. The
Program command A0h is written to any Address
on the first cycle and the second write cycle latch-
es the Address on the falling edge of WF or EF and
the Data to be written on the rising edge and starts
the P/E.C. Read operations within the same bank
output the Status Register bits after the program-
ming has started. Memory programming is made
only by writing '0' in place of '1'. Status bits DQ6
and DQ7 determine if programming is on-going
and DQ5 allows verification of any possible error.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded Cycles. A fourth write operation latches the
Address and the Data to be written and starts the
P/E.C. Read operations within the same bank out-
put the Status Register bits after the programming
has started. Memory programming is made only
by writing '0' in place of '1'. Status bits DQ6 and
DQ7 determine if programming is on-going and
DQ5 allows verification of any possible error. Pro-
gramming at an address not in blocks being
erased is also possible during erase suspend.
Double Word Program (DPG) Instruction. This
feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel. High voltage (11.4V to 12.6V) on V_PP
pin is required. This instruction uses five write cy-
cles. The double word program command 40h is
written to address 555h on the third cycle after two
Coded Cycles. A fourth write cycle latches the ad-
dress and data to be written to the first location. A
fifth write cycle latches the new data to be written
to the second location and starts the P/E.C.. Note
that the two locations must have the same address
except for the address bit A0. The Double Word
Program can be executed in Bypass mode (DPG-
BY) to skip the two coded cycles at the beginning
of each command.
Block Protect (BP), Block Unprotect (BU),
Block Lock (BL) Instructions. All blocks are
protected at power-up. Each block of the array has
two levels of protection against program or erase
operation. The first level is set by the Block Protect
instruction; a protected block cannot be pro-
grammed or erased until a Block Unprotect in-
struction is given for that block. A second level of
protection is set by the Block Lock instruction, and
requires the use of the WPF pin, according to the
following scheme:
– when WPF is at V_IH, the Lock status is overrid-
den and all blocks can be protected or unpro-
tected;
– when WPF is at V_IL, Lock status is enabled; the
locked blocks are protected, regardless of their
previous protect state, and protection status
cannot be changed. Blocks that are not locked
can still change their protection status, and pro-
gram or erase accordingly;
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