M36DR432A Datasheet, PDF (35/46 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36DR432A, M36DR432B
Table 31. SRAM Read AC Characteristics
(T_A = –40 to 85°C; V_DDS = 1.65V to 2.2V)
Symbol
Alt
Parameter
t_AVAV
t_RC Read Cycle Time
t_AVQV
t_AA Address Valid to Output Valid
t_AXQX
t_OH Address Transition to Output Transition
t_BHQZ
t_BHZ UBS, LBS Disable to Hi-Z Output
t_BLQV
t_BA UBS, LBS Access Time
t_BLQX
t_BLZ UBS, LBS Enable to Low-Z Output
t_E1HQZ
t_HZ1 Chip Enable 1 High to Output Hi-Z
t_E1LQV
t_CO1 Chip Enable 1 Low to Output Valid
t_E1LQX
t_LZ1 Chip Enable 1 Low to Output Transition
t_E2HQV
t_CO2 Chip Enable 2 High to Output Valid
t_E2HQX
t_LZ2 Chip Enable 2 High to Output Transition
t_E2LQZ
t_HZ2 Chip Enable 2 Low to Output Hi-Z
t_GHQZ
t_OHZ Output Enable High to Output Hi-Z
t_GLQV
t_OE Output Enable Low to Output Valid
t_GLQX
t_OLZ Output Enable Low to Output Transition
t_PD ⁽¹⁾
Chip Enable 1 High or Chip Enable 2 Low to Power
Down
t_PU ⁽¹⁾
Chip Enable 1 Low or Chip Enable 2 High to Power Up
Note: 1. Sampled only. Not 100% tested.
SRAM
Min
Max
100
100
15
25
100
5
0
30
100
10
100
10
0
25
0
30
35
5
100
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 16. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V_IL
A0-A17
tAVQV
tAXQX
tAVAV
VALID
DQ0-DQ15 DATA VALID
DATA VALID
AI90217
Note: E1S = Low, E2S = High, GS = Low, WS = High.
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