M36DR432A Datasheet, PDF (22/46 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36DR432A, M36DR432B
SRAM COMPONENT
Device Operations
The following operations can be performed using
the appropriate bus cycles: Read Array, Write Ar-
ray, Output Disable, Power Down (see Table 3).
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable (WS) is at V_IH with
Output Enable (GS) at V_IL, and both Chip Enables
(E1S and E2S) and UBS, LBS combinations are
asserted.
Valid data will be available at the output pins within
t_AVQV after the last stable address, providing GS is
Low, E1S is Low and E2S is High. If Chip Enable
or Output Enable access times are not met, data
access will be measured from the limiting parame-
ter (t_E1LQV, t_E2HQV, or t_GLQV) rather than the ad-
dress. Data out may be indeterminate at t_E1LQX,
t_E2HQX and t_GLQX, but data lines will always be val-
id at t_AVQV (see Table 31, Figures 16 and 17).
Write. Write operations are used to write data in
the SRAM. The SRAM is in Write mode whenever
the WS and E1S pins are at V_IL, with E2S at V_IH.
Either the Chip Enable inputs (E1S and E2S) or
the Write Enable input (WS) must be de-asserted
during address transitions for subsequent write cy-
cles. Write begins with the concurrence of both
Chip Enables being active with WS at V_IL. A Write
begins at the latest transition among E1S going to
V_IL, E2S going to V_IH and WS going to V_IL. There-
fore, address setup time is referenced to Write En-
able and both Chip Enables as t_AVWL, t_AVE1L and
t_AVE2H respectively, and is determined by the latter
occurring edge. The Write cycle can be terminated
by the rising edge of E1S, the rising edge of WS or
the falling edge of E2S, whichever occurs first.
If the Output is enabled (E1S=V_IL, E2S=V_IH and
GS=V_IL), then WS will return the outputs to high
impedance within t_WLQZ of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. Data input must be valid for t_DVWH
before the rising edge of Write Enable, or for
t_DVE1H before the rising edge of E1S or for t_DVE2L
before the falling edge of E2S, whichever occurs
first, and remain valid for t_WHDX, t_E1HAX or t_E2LAX
(see Table 32, Figure 19, 21, 23).
Standby/Power-Down. The SRAM chip has a
Chip Enable power-down feature which invokes
an automatic standby mode (see Table 31, Figure
18) whenever either Chip Enable is de-asserted
(E1S=V_IH or E2S=V_IL).
Data Retention
The SRAM data retention performances as V_CCS
go down to V_DR are described in Table 33 and Fig-
ure 23, 24. In E1S controlled data retention mode,
minimum standby current mode is entered when
E1S ≥ V_CCS – 0.2V and E2S ≤ 0.2V or
E2S ≥ V_CCS – 0.2V. In E2S controlled data reten-
tion mode, minimum standby current mode is en-
tered when E2S ≤ 0.2V.
Output Disable. The data outputs are high im-
pedance when the Output Enable (GS) is at V_IH
with Write Enable (WS) at V_IH.
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