M36DR432A Datasheet, PDF (11/46 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36DR432A, M36DR432B
INSTRUCTIONS AND COMMANDS
Seventeen instructions are defined (see Table
15), and the internal P/E.C. automatically handles
all timing and verification of the Program and
Erase operations. The Status Register Data Poll-
ing, Toggle, Error bits can be read at any time, dur-
ing programming or erase, to monitor the progress
of the operation.
Instructions, made up of one or more commands
written in cycles, can be given to the Program/
Erase Controller through a Command Interface
(C.I.). The C.I. latches commands written to the
memory. Commands are made of address and
data sequences. Two Coded Cycles unlock the
Command Interface. They are followed by an input
command or a confirmation command. The Coded
Sequence consists of writing the data AAh at the
address 555h during the first cycle and the data
55h at the address 2AAh during the second cycle.
Instructions are composed of up to six cycles. The
first two cycles input a Coded Sequence to the
Command Interface which is common to all in-
structions (see Table 15). The third cycle inputs
the instruction set-up command. Subsequent cy-
cles output the addressed data, Electronic Signa-
ture, Block Protection, Configuration Register
Status or CFI Query for Read operations. In order
to give additional data protection, the instructions
for Block Erase and Bank Erase require further
command inputs. For a Program instruction, the
fourth command cycle inputs the address and data
to be programmed. For a Double Word Program-
ming instruction, the fourth and fifth command cy-
cles input the address and data to be
programmed. For a Block Erase and Bank Erase
instructions, the fourth and fifth cycles input a fur-
ther Coded Sequence before the Erase confirm
command on the sixth cycle. Any combination of
blocks of the same memory bank can be erased.
Erasure of a memory block may be suspended, in
order to read data from another block or to pro-
gram data in another block, and then resumed.
When power is first applied the command interface
is reset to Read Array.
Command sequencing must be followed exactly.
Any invalid combination of commands will reset
the device to Read Array. The increased number
of cycles has been chosen to ensure maximum
data security.
Table 13. Commands
Hex Code
Command
00h
Bypass Reset
10h
Bank Erase Confirm
20h
Unlock Bypass
30h
Block Erase Resume/Confirm
40h
Double Word Program
Block Protect, or
60h
Block Unprotect, or
Block Lock, or
Write Configuration Register
80h
Set-up Erase
Read Electronic Signature, or
90h
Block Protection Status, or
Configuration Register Status
98h
CFI Query
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded Cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read.
CFI Query (RCFI) Instruction. Common Flash
Interface Query mode is entered writing 98h at ad-
dress 55h. The CFI data structure gives informa-
tion on the device, such as the sectorization, the
command set and some electrical specifications.
Table 18, 19, 20 and 21 show the addresses used
to retrieve each data. The CFI data structure con-
tains also a security area; in this section, a 64 bit
unique security number is written, starting at ad-
dress 80h. This area can be accessed only in read
mode by the final user and there are no ways of
changing the code after it has been written by ST.
Write a read instruction (RD) to return to Read
mode.
Auto Select (AS) Instruction. This instruction uses
two Coded Cycles followed by one write cycle giv-
ing the command 90h to address 555h for com-
mand set-up. A subsequent read will output the
Manufacturer or the Device Code (Electronic Sig-
nature), the Block Protection status or the Config-
uration Register status depending on the levels of
A0 and A1 (see Table 10, 11 and 12). A7-A2 must
be at V_IL, while other address input are ignored.
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