M36DR432A Datasheet, PDF (31/46 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36DR432A, M36DR432B
Table 29. Flash Program, Erase Times and Program, Erase Endurance Cycles
(T_A = –40 to 85°C; V_DDF = 1.65V to 2.2V, V_PPF = V_DDF unless otherwise specified)
Parameter
Min
Max ⁽¹⁾
Typ
Typical after
100k W/E Cycles
Unit
Parameter Block (4 KWord) Erase (Preprogrammed)
2.5
0.15
0.4
s
Main Block (32 KWord) Erase (Preprogrammed)
10
1
3
s
Bank Erase (Preprogrammed, Bank A)
2
6
s
Bank Erase (Preprogrammed, Bank B)
10
30
s
Chip Program ⁽²⁾
20
25
s
Chip Program (DPG, V_PP = 12V) ⁽²⁾
10
s
Word Program
200
10
10
µs
Program/Erase Cycles (per Block)
100,000
cycles
Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or
erase should perform significantly better.
2. Excludes the time needed to execute the sequence for program instruction.
Table 30. Flash Data Polling and Toggle Bits AC Characteristics ⁽¹⁾
(T_A = –40 to 85 °C; V_DDF = 1.65V to 2.2V)
Symbol
Parameter
Flash
Unit
Min
Max
Chip Enable High to DQ7 Valid (Program, EF Controlled)
10
t_EHQ7V
Chip Enable High to DQ7 Valid (Block Erase, EF Controlled)
1
200
µs
10
s
t_EHQV
Chip Enable High to Output Valid (Program)
Chip Enable High to Output Valid (Block Erase)
10
200
µs
1
10
s
t_Q7VQV
Q7 Valid to Output Valid (Data Polling)
0
ns
Write Enable High to DQ7 Valid (Program, WF Controlled)
10
t_WHQ7V
Write Enable High to DQ7 Valid (Block Erase, WF
Controlled)
1
200
µs
10
s
t_WHQV
Write Enable High to Output Valid (Program)
Write Enable High to Output Valid (Block Erase)
10
200
µs
1
10
s
Note: 1. All other timings are defined in Read AC Characteristics table.
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