M36DR432A Datasheet, PDF (17/46 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36DR432A, M36DR432B
Table 17. Status Register Bits ⁽¹⁾
DQ
Name
Logic Level
Definition
Note
'1'
Erase Complete or erase block
in Erase Suspend.
7
Data
Polling
'0'
Erase On-going
Indicates the P/E.C. status, check
during Program or Erase, and on
Program Complete or data of _{completion before checking bits DQ5}
DQ
non erase block during Erase _{for Program or Erase Success.}
Suspend.
DQ
Program On-going ⁽²⁾
6 Toggle Bit
'-1-0-1-0-1-0-1-'
DQ
'-1-1-1-1-1-1-1-'
Erase or Program On-going
Program Complete
Erase Complete or Erase
Suspend on currently addressed
block
Successive reads output
complementary data on DQ6 while
Programming or Erase operations are
on-going. DQ6 remains at constant
level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
5 Error Bit
'1'
Program or Erase Error
This bit is set to '1' in the case of
'0'
Program or Erase On-going
Programming or Erase failure.
4 Reserved
P/E.C. Erase operation has started.
'1'
Erase Timeout Period Expired Only possible command entry is Erase
3
Erase Time
Bit
Suspend (ES)
'0'
Erase Timeout Period On-going
An additional block to be erased in
parallel can be entered to the P/E.C:
2 Toggle Bit
'-1-0-1-0-1-0-1-'
1
Erase Suspend read in the
Erase Suspended Block.
Erase Error due to the currently
addressed block (when DQ5 =
'1').
Program on-going or Erase
Complete.
Indicates the erase status and allows
to identify the erased block.
DQ
Erase Suspend read on non
Erase Suspend block.
1 Reserved
0 Reserved
Note: 1. Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
2. In case of double word program DQ7 refers to the last word input.
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