LSM6DS3H Datasheet, PDF (58/104 Pages) STMicroelectronics – always-on 3D accelerometer and 3D gyroscope

Register description
LSM6DS3H
9.15
CTRL4_C (13h)
Control register 4 (r/w).
Table 54. CTRL4_C register
XL_BW_
SCAL_ODR
SLEEP_G
INT2_on_
INT1
FIFO_
TEMP_EN
DRDY_
MASK
I2C_disable
3.3kHz_
ODR
STOP_ON
_FTH
XL_BW_
SCAL_ODR
Table 55. CTRL4_C register description
Accelerometer bandwidth selection. Default value: 0
(0⁽¹⁾: bandwidth determined by ODR selection, refer to Table 48;
1⁽²⁾: bandwidth determined by setting BW_XL[1:0] in CTRL1_XL (10h) register.)
SLEEP_G
Gyroscope sleep mode enable. Default value: 0
(0: disabled; 1: enabled)
INT2_on_INT1 All interrupt signals available on INT1 pad enable. Default value: 0
(0: interrupt signals divided between INT1 and INT2 pads;
1: all interrupt signals in logic or on INT1 pad)
FIFO_TEMP_EN Enable temperature data as 4^th FIFO data set⁽³⁾. Default: 0
(0: disable temperature data as 4^th FIFO data set;
1: enable temperature data as 4^th FIFO data set)
DRDY_MASK
I2C_disable
Data-ready mask enable. If enabled, when switching from Power-Down to an
active mode, the accelerometer and gyroscope data-ready signals are masked
until the settling of the sensor filters is completed. Default value: 0
(0: disabled; 1: enabled)
Disable I²C interface. Default value: 0
(0: both I²C and SPI enabled; 1: I²C disabled, SPI only)
3.3kHz_ODR
Enable 3.3 kHz in primary SPI interface.
(0: disable; 1: enable 3.3 kHz ODR for gyroscope part with full scale and high-
pass filter coherent with control registers setting).^{(4) (5)}
STOP_ON_FTH Enable FIFO threshold level use. Default value: 0.
(0: FIFO depth is not limited; 1: FIFO depth is limited to threshold level)
1. Filter used in high-performance mode only with ODR less than 3.33 kHz.
2. Filter used in high-performance mode only.
3. This bit is effective if the TIMER_PEDO_FIFO_EN bit of FIFO_CTRL2 (07h) register is set to 0.
4. FIFO and gyroscope low-power mode are not supported when this bit is set to ‘1’.
5. DataReady (pulsed or latched) is available on the INT1/INT2 pins.
9.16
CTRL5_C (14h)
Control register 5 (r/w).
Table 56. CTRL5_C register
ROUNDING2 ROUNDING1 ROUNDING0 0⁽¹⁾ ST1_G ST0_G
1. This bit must be set to ‘0’ for the correct operation of the device
ST1_XL ST0_XL
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