LSM330 Datasheet, PDF (48/75 Pages) STMicroelectronics – Power-down and sleep modes

Register description
LSM330
8.14
STAT (18h)
Interrupt synchronization register (r).
LONG
SYNCW
Table 38. STAT register
SYNC1 SYNC2 INT_SM1 INT_SM2
DOR
DRDY
LONG
SYNCW
SYNC1
SYNC2
INT_SM1
NT_SM2
DOR
DRDY
Table 39. STAT register description
LC interrupt flag.
0 = no interrupt; 1 = Long Counter (LC) interrupt flag common for both SM
Synchronization for external host controller interrupt based on output data
0 = no action waiting from host; 1 = action from host based on output data
0 = SM1 running normally; 1 = SM1 stopped and wait restart request from SM2
0 = SM2 running normally; 1 = SM2 stopped and wait restart request from SM1
SM1- interrupt selection.
1 = SM1 interrupt generated; 0 = SM1 interrupt not generated
SM2- interrupt selection.
1= SM2 interrupt generated; 0 = SM2 interrupt not generated
Data overrun indicates data not read from output register when the measurement of
the next data samples starts. 0 = no overrun; 1 = data overrun
data overrun bit is reset when next sample is ready
data ready from output register.
0 = data not ready; 1 = data ready
8.15
VFC_1 (1Bh)
Vector coefficient register 1 for DIff filter (r/w).
Table 40. VFC_1 default values
0
0
0
0
0
0
0
0
8.16
VFC_2 (1Ch)
Vector coefficient register 2 for DIff filter (r/w).
Table 41. VFC_2 default values
0
0
0
0
0
0
0
0
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