LSM330 Datasheet, PDF (21/75 Pages) STMicroelectronics – Power-down and sleep modes

LSM330
Functionality
Figure 5. LSM330 accelerometer state machines: sequence of state to execute an
algorithm
START
State 1
next
State 2
next
State 3
reset
reset
reset
next
reset
State n
4.2.2
OUTPUT/STOP/CONTINUE
INT set
AM14725v1
FIFO
LSM330 embeds 32 slots of FIFO data for each of the three acceleration output channels
X, Y and Z. This allows consistent power saving for the system, since the host processor
does not need to continuously poll data from the sensor, but it can wake up only when
needed and burst the significant data out from the FIFO. In order to use FIFO it is necessary
to enable the FIFO_EN bit in the CTRL_REG7_A (25h) register.
The FIFO buffer can work accordingly in five different modes: Bypass mode, FIFO mode,
Stream mode, Stream-to-FIFO mode and Bypass-to-Stream mode. Each mode is selected
by the FMODE [2:0] bits in the FIFO_CTRL_REG_A (2Eh) register. Programmable
watermark level, FIFO empty or FIFO overrun events can be enabled to generate dedicated
interrupts on the INT1_A/INT2_A pin (configured through the INT2_EN and INT1_EN bits in
the CTRL_REG4_A (23h) register).
When FIFO is empty, the EMPTY bit in FIFO_SRC_REG_A (2Fh) is equal to '1' and no
samples are available.
If the application requires a lower number of samples, a programmable watermark level can
be set. In FIFO_SRC_REG_A (2Fh) the WTM bit is high if new data arrives and the FSS
[4:0] bit in FIFO_SRC_REG_A (2Fh) is greater than or equal to the WTMP [4:0] bit in the
FIFO_CTRL_REG_A (2Eh) register. In FIFO_SRC_REG_A (2Fh) the WTM bit goes to '0' if
reading X, Y, Z data slot from FIFO and the FSS [4:0] bit in FIFO_SRC_REG_A (2Fh) is less
than or equal to the WTMP [4:0] bit in the FIFO_CTRL_REG_A (2Eh) register.
When FIFO is completely full, the OVRN_FIFO bit in the FIFO_SRC_REG_A (2Fh) is equal
to '1' and the FIFO slot is overwritten.
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