LSM330 Datasheet, PDF (16/75 Pages) STMicroelectronics – Power-down and sleep modes

Module specifications
LSM330
2.4
Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and T_OP.
Symbol
Table 6. SPI slave timing values
Parameter⁽¹⁾
Value⁽²⁾
Min
Max
Unit
t_c(SPC)
SPI clock cycle
100
ns
f_c(SPC)
SPI clock frequency
10
MHz
t_su(CS)
CS setup time
6
t_h(CS)
CS hold time
8
t_su(SI)
SDI input setup time
5
t_h(SI)
SDI input hold time
15
ns
t_v(SO)
SDO valid output time
50
t_h(SO)
SDO output hold time
9
t_dis(SO)
SDO output disable time
50
1. Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A / SDO_G.
2. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results. Not
tested in production.
Figure 3. SPI slave timing diagram
CS ₍₂₎
SPC (2)
t_su(CS)
SDI (2)
SDO (2)
t_c(SPC)
t_su(SI)
t_h(SI)
M SB IN
t_v(SO)
M SB OUT
t_{h(SO )}
(2)
t_h(CS)
(2)
LSB IN
(2)
t_{dis(SO )}
LSB O UT
(2)
Note:
2. Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A / SDO_G.
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output
ports.
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