83C795 Datasheet, PDF (98/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES
83C795
F rames that extend to the buffer des ignated by
R S T OP are continued in the buffer des ignated by
R S T AR T andsucces s ivelocations. R S T OP may be
either greater than R S T AR T +1 or les s than
R S T AR T. Making R S T OP equal to R S T ART or
R S T AR T + 1 leads to unpredictable res ults . T he
relations hip of thes e registers to ring placement in
memory is illus trated in F igure 8-3.
Up to 254 buffers can be allocated to the ring. T he
receiver DMA will us e as many as requiredto s tore
a packet. T his allows the chip to be configured to
receive frames nearly as long as 64K bytes. T his
can be us eful in cus tomiz ed CS MA networks ;
however, allocating s o many buffers to the
reception proces s leaves very little capability for
buffering trans mit frames although it is within the
capability of the 83C795.
T he receive DMAutilizes twoadditional regis ters to
managethebuffer ring. T hes earetheCurrent Page
R egis ter (CUR R ) and the Boundary Page R egis ter
(BOUND). T he CUR R R egis ter points to the firs t
buffer that is not part of a completely received
packet. When R DMAis s toringaframe, this regis ter
points to the s tart of the frame being s tored. When
R DMA is not s toring a frame, it points to the firs t
buffer that will be used for the next frame to be
received.
T he BOUND R egis ter protects received frames
from being overwritten by later frames . It points to
thefirst buffer in theringthat is not tobeoverwritten.
FIGURE 8-3. RING BUFFER STRUCTURE
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