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83C795 Datasheet, PDF (59/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller | |||
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83C795
HOST INTERFACE SECTION
1. Make sure the system address is even. If the
address comes out odd, transfer one byte.
2. Set the STAG bit (ICR.6). This forces a â1â into
bit 0 of the Buffer Counter when the address
is loaded
NOTE
This only happens on a cache miss.
T his makes it pos sible for the host to perform an
even-to-even transfer, but the internal addres s to
the local R AM is trans formed to an odd addres s .
6.1.3 Operation on Micro-Channel Adapters
Do not use this chipfor micro-channel applications .
A future variant may be created with the necess ary
interface logic.
6.2 I/O-MAPPED PIPE
T he I/O-mapped pipe provides another method for
acces s ing the local buffer R AM. When enabled, all
memory acces s es take place through two I/O
regis ters in the hos t interface I/O s pace (IOPL and
IOP H). T he data in thes e two I/O locations
corres ponds to the the location in the buffer
memory indicatedby the Buffer Counter. When run
in this mode, the memory-space addres s decoders
are disabled, s o the adapter will not us e any hos t
memory space for the buffer R AM.
T he mechanis m us ed by the I/O-pipe is similar to
that us edby the memory cache except for address
handling. In this method, the addres s is loadedinto
the Buffer Counter by performing two cons ecutive
writes to the IOPAregis ter. T he firs t write stores the
lower half of the address into a temporary register.
T he secondwrite s tores datadirectly into the upper
half of the buffer counter and moves the temporary
regis ter into the lower half. Any acces s to the chip
between thetwowrites will causethes tatemachine
to not load the address . T he Host Counter is not
us ed during this proces s .
To us e the I/O-pipe, the IOPE N bit (ICR .4) mus t be
s et to 1, and the ME NB bit (CR .6) mus t be s et to 0.
All 8-bit trans fers must take place through IOPL
only. Als o, it is imperative that when s witchingfrom
R ead Mode to Write Mode, the addres s mus t be
reloadedeven if thecounter holds thecorrect value.
6.3 ADDRESS DECODERS
T hree addres s decoders are us ed to detect hos t
acces s es to the buffer memory, I/O regis ters, and
IPL R OM. T hesedecoders obs ervetheS A19-S A05
lines to decode acces s within arange of addres s es
(a window). T he buffer and IPL R OM decoders
allowplacement of their res pective windows on any
8K boundary between C0000H and E F F F F H
regardles s of window size. T his allows windows to
s tart on even or odd 8K boundaries . T he R AM and
IPL R OM are s crollable (and therefore can be
paged) through their programmablewindows izeas
s hown in Table 6-1 below.
DECODER
BUFFER
MIN
BASE
C0000H
IPL ROM
I/O BASE
C0000H
0200H
MAX
BASE
EE000H
EE000H
E3E0H
INCREMENT
2000H
2000H
20H, 2000H
WINDOW
SIZES
8K
16K
32K
64K*
DISABLED
8K
16K
32K
DISABLED
32 Bytes
TABLE 6-1. HOST INTERFACE ADDRESS DECODERS
* Plug and Play cannot utilize this window s ize.
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