83C795 Datasheet, PDF (83/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
LAN CONTROLLER OVERVIEW
7.4 MAC RECEIVER
7.4.1 Basic Functions
T he 83C795’s receiver section process es a s erial
s tream of NR Z data. T he s tart of the frame is
identified, des tination addres s is checked agains t
the s tation addres s , recogniz ed fr ames are
trans ferred to memory and checked for valid
formation. E rror conditions are reported.
7.4.2 Interface to the MAC Receiver
T he s erial interface to the MAC receiver s ection is
handled by four signals : Carrier S ens e (XCR S ),
Collision Detect (XCOL), R eceive Data (XR XD),
and R eceive Clock (XR XC). T he group may come
from one of three s ources :
• internally from the Manchester Decoder
• direct from the pins
• internally from the transmit section.
All sources are treated equally. S election of s ource
is done by programming configuration regis ters .
R efer to the T CON and MANDIS R egis ters for
further information.
Note
These signals are multiplexed with the
IRQ pins and are used for testing pur-
poses only.
7.4.3 Loopback Paths
T he 83C795 has 3 loopback modes .
Mode 1 provides the path between receiver and
trans mitter ins ide the LAN controller. In this mode,
NR Z data from the trans mitter connects to the
receiver’s R X D input, bypas s ing Manches ter
encoder/decoder. XR XC is generated internally for
this mode by dividing 20 Mhz clock by two. T he
minimum frame length for mode 1 loopback is 25
bytes .
Mode2 connects trans mit andreceivedatathrough
the Manches ter encoder/decoder. T he s erial data
is wrapped around jus t inside the device pins with
neither AUI nor T P interfaces actually driving the
outs ide world. T he minimumframe length for mode
2 loopback is 25 bytes .
Mode 3 has trans mitter and receiver pins active
with loopback pins inactive. T he DMAcontroller will
run its s pecial loopback code to allow reception of
theoutgoingtrans miss ion if itis echoedback. In this
mode, the DMA can handle delay of the echo
provided that the frame’s length exceeds echo
delay by at leas t 200 bit times (25 bytes ). When run
in this mode, the board being tes ted should be
connected to an 802.3-compliant cable. T hat cable
may or may not have other 802.3 nodes attached.
Note
Caution is advised when running this
test on a live network or when other
nodes on the test cable could send a
frame to the node under test. Reception
of a frame destined to the loopback
node could confuse the results of the
loopback test as the node will be able
to receive the incoming frame.
7.4.4 Receive Deserialization
R eceive des erializer is activated by carrier s ens e.
Byte alignment is determined by a synch circuit
which detects the S tart-of-F rame Delimiter (S F D)
when it s ees the serial s equence ’10101011’ after
the start of carrier s ens e. T his pattern marks the
firs t octet boundary and determines byte alignment
for the entire frame.
Incoming R XD bits are clocked into an 8 bit wide
s erial-to-parallel s hift regis ter. T hebits arereceived
in order from leas t s ignificant to mos t s ignificant
within each byte. When an octet is complete,
parallel datais loadedintothereceiver F IF O. When
Carrier is los t, the frame is considered to have
terminated; and all remaining s erial data are
dropped. S erial datais pas s edto the CR C checker
which is initialized upon recognition of the S F D.
T his proces s ordinarily dis cards all bits that
precede the S F D pattern without prejudicing
reception of the frame. S ome exceptions can be
made to this proces s to improve the robustnes s of
the receiver. T hey are dis cus s ed below.
T here is a s electable mode (us ing the R CON.R CA
bit) during the receiver operation which adds
robus tnes s by monitoring the X COL s ignal
continuous ly throughout reception, s tarting after
the S tart-of-F rame delimiter. If collision is detected,
reception of the frame is aborted.
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