83C795 Datasheet, PDF (36/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

ETHERNET SYSTEM CONTROLLER REGISTERS
83C795
5.2 LAN CONTROLLER REGISTER
DESCRIPTIONS
To s implify the programming model for the LAN
controller and retain compatibility with the S MC
83C690 LAN Controller, the internal regis ters are
dividedintotwoaddres s maps . T hedefault address
map is us ed for R ing-s tyle buffering (like the
83C690). T hos e regis ters needed for linked-lis t
buffering are grouped together in the alternate
addres s map and are enabled through the
E nhancement (E NH) regis ter des cribeds tarting on
page 26.
E ach map provides acces s to all regis ters
neces s ary for operating that particular buffering
mode. Many registers are vis ible in both maps ,
although not always at the s ame addres s in each.
To facilitate manufacturing test of the device, many
internal regis ters can be acces sedin one or both of
thes e maps . Within each map, the regis ters are
organized into 4 pages of 16 regis ters each. Only
onepageis vis ibleat atime. Pages election is made
through the Command (CMD) regis ter described
s tarting on page 24.
T he addres ses lis ted in this s pecification are in an
abbreviated form. T he firs t hex digit is really a
two-bit ’page’ value which is written into the LAN
COMMAND (CMD) regis ter to acces s the 16
regis ters visible for that page. T he digits after the
colon are the offs et within the 83C795’s L AN
Controller I/O s egment in this manner:
page:offset
To determine the correct addres s , you mus t firs t
know the 83C795’s base addres s then s elect the
correct pageandfinally s elect thecorrect offset. S o,
for example, "3:1C" indicates that the addres s for
this particular regis ter is found on page 3 at the
offs et value 1C.
In thefollowingdes criptions , themos t significant bit
position is numbered ’7’. T he line labelled R E S E T
s hows the initial values loaded into the regis ter by
as sertion of theR E S E T pin. T hesymbol ’0’denotes
void bits which always return zero when read.
5.2.1 ALICNT - Alignment Error Counter
Register
Normal MapR eadPort = 0:1D Link-List MapR ead
Port = 0:1D
T his register is the alignment error counter. It is
incremented by the receive unit when a packet is
receivedwith aframealignment error. Only packets
whose addres ses are recognized will be included
in this tally. T he counter will increment to 255 and
s topif additional alignment errors aredetected. T he
counter is cleared when read.
BIT
7 CT7
6 CT6
5 CT5
4 CT4
3 CT3
2 CT2
1 CT1
0 CT0
ALICNT
RESET
0
0
0
0
0
0
0
0
5.2.2 BOUND - Receive Boundary Page
Register
Normal Map R ead/Write Port = 0:13
T he R eceive Boundary Page R egis ter points to the
oldest us ed receive buffer in the ring. It is us ed to
prevent overflow in the buffer ring. T he DMA
compares the contents of this register to the next
buffer addres s when linking buffers together for
s torage of a received frame. If the contents match
the next buffer addres s , the DMA operation is
aborted. Only A08-A15 are s pecified s ince all
buffers are aligned on 256-byte boundaries . F or
more information, refer to page 85.
BIT
7 A15
6 A14
5 A13
4 A12
3 A11
2 A10
1 A09
0 A08
BOUND
RESET
X
X
X
X
X
X
X
X
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