83C795 Datasheet, PDF (20/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

PIN LIST
83C795
Mnemonic Pin Number I/O
LA17-LA23 13-19
I/O
LLED
131
I/O
M16CS
26
O
MA15-MA10 139-144
O
MA09/JMP9 145
I/O
MA08/JMP8 146
MA07/JMP7 148
MA06/JMP6 149
MA05/JMP5 150
MA04/JMP4 151
MA03/JMP3 152
MA02/JMP2 153
MA01/JMP1 154
MA00/JMP0 155
MD7
158
I/O
MD6-MD0 3-9
ME MR
12
I/O
ME MW
10
I/O
OS R
112
I
R AMOE
156
O
R AMWR
157
O
RESET
95
I/O
Description
PC LA ADDR E S S BUS . Advanced timing vers ion of s ys tem
addres s lines A23-A17 from PC/AT bus . T hese are not as s umed to
be s table during the entire hos t cycle and are latched internally by
the BALE signal (falling edge). T hese s ignals are active high.
T WPR LINK S TAT US . If valid data or Link Tes t puls es are received
on T PR + / T PR -, LLE D is low (link s tatus OK). When no data or
Link Tes t puls es are received, LLE D is high. T he LLE D pin can
sink 4mA to drive an external LE D. T his pin als o functions as the
E E R OM clock pin (formerly E E S K) and functions as the s hift
control pin (formerly S HIF T IN) in scan mode.
ME MOR Y 16 S E LE CT E D. Active low. Indicates to the PC/AT bus
that R AM acces s res pons e is 16 bits wide.
ME MOR Y ADDR E S S LINE S . T hese pins bring out the DMA
addres s to memory or feed-through the hos t addres s as modified
for paging. When dumping R OM contents , thes e pins pres ent
R OM data bits :
MA15 R OM30 then R OM31
MA14 R OM28 then R OM29
...
MA00 R OM00 then R OM01
S ame as other MA lines except that during R E S E T, the drivers are
disabled and the INIT jumpers are read through thes e pins and
latched at the trailing edge of R E S E T. T hey are active high and are
pulled up weakly by internal res is tors (35kΩ –150kΩ).
To s et a zero value on thes e pins , us e an external pull-down
res is tor of 3.6KΩ.
ME MOR Y DAT A LINE S . T hese pins connect to the data pins of the
buffer R AM and the IPL or boot R OM.
PC ME MOR Y R E AD for addres s es exceeding 1 M. Active low.
PC ME MOR Y WR IT E for addres s es exceeding 1 M. Active low.
VCO BIAS R E S IS T OR . A res is tor from OS R to VCC bias es the
internal VCO current. Nominal value is 24.9KΩ..
R AM OUT PUT E NABLE . Active low.
R AM WR IT E E NABLE . Active low.
S YS T E M R E S E T. Active high.
TABLE 4-1. 83C795 PIN ASSIGNMENTS (CONT.)
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