83C795 Datasheet, PDF (10/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

GENERAL DESCRIPTION
83C795
1.0 GENERAL DESCRIPTION
T he S MC 83C795 E thernet S ys tem Controller
implements the IE E E 802.3 protocol for networks
s uch as E thernet, Cheapernet, and10BaseT. It is a
highly integrateddevice that s hrinks thees senceof
a LAN adapter card onto a s ingle piece of s ilicon. It
includes the 802.3 Media Access Control (MAC)
functions, the Phys ical Layer Interface (PLI) for
10BAS E -T media, andahos t interfacedes ignedfor
s imple connection to the I ndus try S tandard
Architecture (IS A) PC/AT bus.
To create a LAN adapter only the 83C795, a single
buffer R AM, an E E R OM chip, andan optional R OM
for B IOS or IP L code s torage are required.
T ransformers and s upporting analog components
complete an adapter des ign. All neces s ary control
logic is provided by the 83C795.
T he resulting LAN adapter appears to the hos t as
a block of I/O regis ters with a block of s hared
memory, unles s the I/O pipe is us ed. T he base
address for I/O regis ters is programmable as is the
base addres s and s ize of the buffer memory.
T his device is s imilar to the S MC 83C790 LAN
controller with three major differences:
• A small memory cache has been added for host
accesses to shared memory.
• An I/O pipe mode has been added to access the
buffer memory.
• Auto-configurability logic has been added in
order to comply with the new ISA Plug and Play
specification.
As with the83C790 chip, therearetwobasicmodes
of operation: normal and ALT E GO. In the normal
mode, the LAN controller operates much like the
83C690 LAN Controller with receivedframes being
buffered in a ring of contiguous , fixed-s ize buffers .
When the ALT E GO feature is enabled, the device
s witches to a very different mode of operation. T he
differences are s ummarized here and explained in
detail throughout the s pecification:
1. Linked-list style of buffering instead of ring
buffers.
2. Different register map for LAN controller, ex-
posing new registers for the linked-list buff-
ering.
F igure 1-1 depicts the 83C795’s functionality.
2.0 FEATURES
T he bas ic features of the 83C795 chip are
s ummarized here:
• Memory caching with time-shared access to
buffer RAM.
• Compliant with the ISAPlug And Play specification
• Software compatible with 83C790 drivers
• Direct interface with ISA bus without TTL buffers
• I/O-mapped pipe access to buffer RAM
• Extended length option for the twisted-pair port
• Underrun detection in early receive mode
• Staggered address transfers supported
• Ring-empty bit supplied to host
• Automatic ring-wrapping
• PC-98 bus support through addition of a jumper
• Buffered 20 MHz clock output available through
addition of a jumper
• Support for diskless workstations via Initial
Program Load ROM
• Programmable base address and window size
for buffer memory and IPL ROM
• Support for paging of buffer memory and IPL
ROM
• Programmable I/O base address
• Programmable bus width of either 8 or 16 bits
• Zero wait state operation
• Automatic loading of host interface
configuration and LAN address from external
serial EEPROM
• Separate address and data busses to memory
with no external address latches
• 7 programmable interrupt levels
• Clock oscillator
• Full 802.3 MAC layer protocol implementation
with extended features
• Support for transmission and reception of
frames up to 32K bytes long
• Transmit frame start at any location - no word
alignment required
• Two modes of frame buffering: 83C690 mode
and descriptor table mode
• Loopback modes - internal and external
• Full-duplex DMA capability in loopback mode
• Built-in AUI serial interface including drivers and
receivers
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