83C795 Datasheet, PDF(95/136 Page) List of Unclassifed Manufacturers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

83C795 Datasheet, PDF (95/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

◁

83C795

BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES

completion of the trans mit chain. Normal mas king

applies on top of this delay mechanism.

Without enabling this new mode of controlling

trans mit interrupts, an interrupt will begeneratedon

a frame by frame bas is but the interrupt s tatus may

notbecurrent by thetimeitcan bereadby thedriver

s oftware.

8.1.2.1 Ownership of Buffers

T he T S T AT fieldof the table entry is us ed to control

owners hip of the frame buffers . Hands hake over

control of trans mit frame buffers is governedby the

following conventions :

TSTAT Field Value

Meaning

TSTAT field = 00

83C795 has begun

transmission.

TSTAT field > 00 and < Frame completed.

FFh

TSTAT field = FF

Assembled frame,

not yet transmitted.

TABLE 8-1. TSTAT FIELD VALUES

T he driver s oftware fills the T S T AT table entry with

F F hwhen itreleas es theframetotheLAN controller

for trans mis s ion. When trans mit command has

been s et and device is online, the DMA looks at

T S TAT field. If it encounters a field = F F, it will

attempt totransmit theframepointedtoby theentry.

T he s tatus field will be changed to zero after

descriptor entry is read and trans mitter commits to

s ending. If DMA encounters a T S T AT field greater

than or les s than FF h, no frame will be transmitted,

the trans mit complete interrupt will be sent. T he

field is not altered.

When a transmis sion completes, the contents of

T S TAT regis ter will be moved into that location.

8.1.2.2 Modifying the Transmit Queue

To add a frame to the transmit queue, build the

frame in buffer memory then find the table entry

following the las t enqueued frame. E nter the

descriptor for the new frame with a T S T AT that is

neither 00 nor F F in value. When des criptor is

complete, writeT S T AT with FF. T hedes criptor entry

following the las t enqueued frame entry must have

its T S TAT value marked with a non-F F value. T hat

defines the end of the enqueued frames for the

DMA.

S et theT XP bit of theCOMMAND register toens ure

that thenewtrans mis s ion goes out. T heT XP bit can

be written regardless of completion status and will

ensure that the latest frame does get trans mitted. If

the LAN controller reaches the end of the trans mit

queue before the new frame has been added, a

trans mit complete interrupt is generated for the old

portion of thequeue andanother trans mit complete

interrupt will be generated when the added portion

completes .

T he driver s hould not attempt to alter any buffered

frame whos e T S T AT is either 00 or F F while

CMD.T XP is turned on. Wait until all trans mis s ions

are complete or set the CMD.S T P bit and wait for

the S T OP status to be confirmed in the Interrupt

S tatus regis ter. E xamine T S T AT table entries to

determine which frames have been transmitted.

T hos e whose entries areF F have not been opened

by trans mitter.

R efer to Tables 8-2 and 8-3 for a s ummary of the

trans mit descriptor table format.

8-BIT MEMORY

16-BIT MEMORY

COLCNT

TSTAT

TSTARTL

TSTARTH

TCNTL

TCNTH

TCON

not used

D15-D08