83C795 Datasheet, PDF (93/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES
8.0 BUFFER STRUCTURING AND DATA
MOVEMENT PROCESSES
8.1 TRANSMIT PACKETS
8.1.1 Single Packet Transmission
A packet for transmis sion is placed by the hos t into
buffer memory. T his packet must include the DA,
S A, and data fields. T he preamble, S F D, and CR C
(normally) are not included in the buffer. If CR C
generation is s uppress ed, the CR C field for the
packet is also s upplied by the hos t. T he packet is
placed in a contiguous block of memory in the
buffer, s tarting on a 256-byte boundary.
Valid 802.3 packets have at least 48 bytes of data.
If les s datais tobetrans mittedon an 802.3 network,
it is the res pons ibility of the host to build a packet
with pad data included. T he 83C795 will transmit
frames of any programmed length (greater than 17
bytes), even thos e which are too s hort to be valid
frames in an 802.3 network. DMA will trans fer the
number of bytes programmed into the T CNT H and
T CNT L R egis ter pair s tarting fr om addres s
(T S TAR T * 100H).
8.1.2 Multiple Packet Transmissions
To s upport multiple trans mis s ions per command, a
trans mit queue can be enabled by s etting the
ALT E GObit in theE nhancement R egis ter (E NH.5).
In this mode, a table of frame descriptors defines
the s tarting location and length of all enqueued
trans miss ions . T his des criptor table is process edin
a circular manner by the LAN controller.
T he table is treated as a ring of entries whose
s tarting and ending points are defined by a pair of
regis ter s (T B E GI N and T E ND) in the L AN
controller. T hes e regis ters are initialized with the
upper 8-bits of address for the firs t location of the
table andthe first location after the endof the table.
T E ND is not within thetable. When tableproces sing
reaches thelocation definedby T E ND, it is s witched
back to T BE GIN. T he table mus t be aligned with
256 byteboundary in thebuffer memory. E ach entry
is 8 bytes long. T he format of this buffering is
defined in F igure 8-1.
Tos endmultipletrans mis s ions, thedriver builds the
frames in buffer memory in the same contiguous
form pres ently expected. T he driver then adds an
entry for each frame into a table of trans mit
descriptors . T his entry contains thes tartinglocation
and length, and trans mit configuration for each
frame in the trans mit queue. Places are providedin
the table for return of the T rans mit S tatus (T S T AT )
R egis ter and collision count ass ociated with each
trans miss ion. A simple s emaphore protocol will be
us ed to control ownership of trans mit buffers .
T he LAN controller keeps a pointer in the T T ABH
and T T ABL R egis ters to the trans mit descriptor
table. T his pointer is initialized by the driver when
the table is firs t built and s hould not need
re-initializationthereafter. When transmit command
has been s et and device is online, trans mit begins
from the entry pointed to by the T T ABH and T T ABL
R egis ters . T he LAN controller firs t checks the
T S T AT field. If it encounters a field equal to F F, it
will attempt to trans mit the frame pointed to by the
entry. T he s tatus field will be changed to zero after
the remainder of the entry has been read. When it
encounters a T S T AT field not equal to F F, no frame
will be s ent, the trans mit complete interrupt will be
s ent and the field will not be altered.
If the frame is marked for trans mis s ion, the DMA
controller loads its T S T AR T H, T S T AR T L, T CNT H,
T CNT L, and T CON R egis ters from the des criptor.
T S T AT gets marked as havingbeen opened by the
LAN controller and trans mis s ion proceeds as with
s ingle tr ans mis s ions except that when the
trans miss ion has completed, the trans mit status
and collision count are moved by DMA into the
table. T hetablepointer is updatedandtransmis sion
of next entry begins.
If a transmit abort occurs (too many collis ions ) the
trans mitter will stop proces s ing the chain and pos t
the current trans mit and interrupt s tatus . If the
CMD.S T P bit is s et, the trans mis s ion of any
ongoing frame proceeds until completion or abort
but no s ucces s ive fr ames in the chain are
process ed. T he T T AB indices will point to the firs t
unproces s ed frame in the table s o that none are
los t.
An alternative mode of controlling the transmit
interrupt can be enabled by the E OT INT bit in the
E nhancement (E NH) R egis ter. When enabled, the
trans mit interrupt will be generated only upon
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