83C795 Datasheet, PDF (64/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

HOST INTERFACE SECTION
83C795
6.5 MEMORY BUS STRUCTURE AND
CONFIGURATION
6.5.1 Memory Bus Width Control
Becaus e of the 83C795’s memory cache, the width
of the memory path is fixed at 8 bit. By means of
the memory cache, the I/O pipe can service either
an 8-bit or 16-bit hos t acces s . T he Hos t and hos t
interface logic are programmed for a s pecific
memory width by s etting bit 7 in the BIOS Page
R egis ter, M16E N. (S ee page 17 for more on this
bit.)
T he 83C795 calculates the width of the hos t bus by
observingtheME MR linefor trans itions . An internal
flag (E E R OM.HOS T 16) is s et to indicate a 16-bit
host bus after 2 ris ing edges are s een on this pin.
When connected to an 8-bit hos t, this pin is left
unconnected or is tiedto VDD and s hould not have
any trans itions .
6.5.2 16-Bit Response To Host Access
T he BPR .M16E N bit in the BIOS Page R egis ter
tells the hos t interface logic whether to make the
L AN adapter res pond as a 16-bit or an 8-bit
peripheral to the hos t. T he 83C795 res ponds to
either hos t bus width.
When the hos t acces s es memory, an addres s
comparator within the 83C795 looks at the
LA23-L A17 lines to determine if the 83C795’s
memory territory is being acces s ed. If it is and if
MPR .M16E N is s et, the M16CS line is activated to
tell the hos t to run a16-bit trans fer cycle. When this
decision is bas ed only on the LA addres s lines, it is
poss ible that the M16CS will be s ent out when the
host is access ingadeviceother than 83C795 within
the s ame addres s range.
To allow finer resolution for the M16CS decode,
thereis an optional means of includingthedecoding
of S A16-S A13 lines in thegeneration of theM16CS
res pons e. T his can be enabled by the FINE 16 bit
of theMemory PageR egis ter. Becaus etheS Alines
are not guaranteed s table as early as LA lines , this
form of decoding can lead to erroneous res ults .
Be careful when you us e this method. To avoid bus
width conflicts between buffer memory and the
R OM as well as conflicts with other cards in the
s ystem, the16-bit response s houldbe turnedon by
s oftware only when that s oftware can guarantee
that no access to the R OM is taking place and that
the only acces s es within the 128K memory range
are to 16-bit devices . T his may mean ens uring that
no acces s to any other card can take place. In
exis tingdrivers , this is doneby performingall 16-bit
trans fers within interrupt s ervice routines that keep
all other interrupts disabled during the trans fer.
Take s pecial care when writing IPL R OM code. If
the code actually gets executed out of R OM, the
R OM can potentially be configuredwithin the same
128K block. T he best advice is to copy code from
R OM to s ys tem memory outs ide the block or to
write code that does not enable 16-bit trans fers .
T he Hos t is provided with the ZWS s ignal in
accordance with whether the memory cache can
accommodate the trans fer. T he timingof this signal
is dependent upon the width of the trans fer being
performed with the host.
Tomeet thememory bandwidth requiredby theIS A
bus, it is necess ary toimplement thebuffer memory
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