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83C795 Datasheet, PDF (51/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller
83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
5.2.42 TLEVEL - Transmit FIFO Track Register
Normal Map R ead Port = 3:1E
Linked-List Map R ead Port = 3:1E
T his counter tracks the number of empty bytes in
the trans mit FIFO. An empty F IF O has 10h in this
counter. A full F IF O has 00h.
BIT
7—
6—
5—
4 CT04
3 CT03
2 CT02
1 CT01
0 CT00
TLEVEL
RESET
0
0
0
0
0
0
0
0
5.2.43 TSTARTH - Transmit Start Page High
Register
Normal Map R ead Port = 2:14
Normal Map Write Port = 0:14
T his regis ter is the higher 8 bits of a regis ter pair
that points to the as s embled packet to be
trans mitted. To retain compatibility with 83C690
drivers, the us er s houlds tart all frames on 256-byte
boundaries and not write to T S T ART L.
BIT
7 A15
6 A14
5 A13
4 A12
3 A11
2 A10
1 A09
0 A08
TSTARTH
RESET
0
0
0
0
0
0
0
0
5.2.44 TSTARTL - Transmit Start Page Low
Register
Normal Map R ead/Write Port = 3:15
Linked-List Map R ead/Write Port = 3:15
T his regis ter is thelower 8 bits of aregis ter pair that
points to the as sembled packet to be transmitted.
Toretain compatibility with83C690 drivers, theus er
s hould s tart all frames on 256-byte boundaries and
only write to the T S T ART H register.
BIT
7 A07
6 A06
5 A05
4 A04
3 A03
2 A02
1 A01
0 A00
TSTARTL
RESET
0
0
0
0
0
0
0
0
5.2.45 TSTAT - Transmit Status Register
Normal Map R ead Port = 0:14
Linked-List Map R ead Port = 0:14
T he T rans mit S tatus R egis ter reports events that
occur on the media at the end of packet
tr ans mi s s ion. All bits are cleared prior to
trans miss ion of a packet and are s et as needed.
When ALT E GO = 1, the regis ter is cleared only at
the beginning of a transmit chain and is s et after
each packet has completed.
BIT
TSTAT
7 OWC
6 CDH
5 UNDER
4 CRL
3 ABORT
2 TWC
1 NDT
0 PTX
RESET
0
0
0
0
0
0
0
0
Bit 7: OWC, Out of Window Collision
T his bit is set if acollision is detectedmorethan one
s lot time after the start of trans miss ion. T ransmis -
s ion is aborted under thes e conditions .
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