COM20020I_0609 Datasheet, PDF (66/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Never change the CKP3-1 when the data rate is over 5 Mbps. They must all be zero.
C) Shorten The Write Interval Time To The Command Register
The COM20020I 3V limits the write interval time for continuous writing to the Command register. The minimum interval
time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 μS at the 156.25 Kbps. This 1.6 μS is very long
for CPU.
Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to XTAL clock which
is not changed by the data rate, such that the minimum interval time becomes 100 nS.
D) Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands
The COM20020I 3V has a write prohibition period for writing the Enable Transmit/Receive Commands. This period is
started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by setting the TA/RI bit with
a pulse signal. It is 3.2 μS at 156.25 Kbps. This period may be a problem when using interrupt processing. The
interrupt occurrs when the RI bit returns to High. The CPU writes the next Enable Receive Command to the other page
immediately. In this case, the interval time between the interrupt and writing Command is shorter than 3.2 μS.
Setting the EF bit will cause the TA/RI bit to return to High upon release of the pulse signal for setting the TA/RI bit,
instead of at the start of the pulse. This is illustrated in Figure 29.
EF=0
TA/RI bit
Setting Pulse
nINTR pin
EF=1
TA/RI bit
Setting Pulse
nINTR pin
Tx/Rx completed
prohibition period
Tx/Rx completed
Figure 29 - Effect Of The EF Bit On The TA/RI Bit
SMSC COM20020I 3.3V Rev.E
Page 66
DATASHEET
Revision 09-11-06