COM20020I_0609 Datasheet, PDF (18/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
High Speed CPU Bus Timing Support
High speed CPU bus support was added to the COM20020I 3V. The reasoning behind this is as follows: With the
Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read
signal is active and remain after the read signal is inactive. But the High Speed CPU bus timing doesn't adhere to
these timings. For example, a RISC type single chip microcontroller (like the HITACHI SuperH series) changes I/O
address at the same time as the read signal. Therefore, several external logic ICs would be required to connect to this
microcontroller.
In addition, the Diagnostic Status (DIAG) register is cleared automatically by reading itself. The internal DIAG register
read signal is generated by decoding the Address (A2-A0), Chip Select (nCS) and Read (nRD) signals. The decoder
will generate a noise spike at the above tight timing. The DIAG register is cleared by the spike signal without reading
itself. This is unexpected operation. Reading the internal RAM and Next Id Register have the same mechanism as
reading the DIAG register.
Therefore, the address decode and host interface mode blocks were modified to fit the above CPU interface to support
high speed CPU bus timing. In Intel CPU mode (nRD, nWR mode), 3 bit I/O address (A2-A0) and Chip Select (nCS)
are sampled internally by Flip-Flops on the falling edge of the internal delayed nRD signal. The internal real read signal
is the more delayed nRD signal. But the rising edge of nRD doesn't delay. By this modification, the internal real
address and Chip Select are stable while the internal real read signal is active. Refer to Figure 4 below.
A2-A0, nCS
VALID
nRD
Delayed nRD
(nRD1)
Sampled A2-A0, nCS
More delayed nRD
(nRD2)
VALID
Figure 4 - High Speed Cpu Bus Timing - Intel CPU Mode
The I/O address and Chip Select signals, which are supplied to the data output logic, are not sampled. Also, the nRD
signal is not delayed, because the above sampling and delaying paths decrease the data access time of the read
cycle.
The above sampling and delaying signals are supplied to the Read Pulse Generation logic which generates the
clearing pulse for the Diagnostic register and generates the starting pulse of the RAM Arbitration. Typical delay time
between nRD and nRD1 is around 15nS and between nRD1 and nRD2 is around 10nS.
Longer pulse widths are needed due to these delays on nRD signal. However, the CPU can insert some wait cycles to
extend the width without any impact on performance.
The RBUSTMG bit was added to Disable/Enable the High Speed CPU Read function. It is defined as: RBUSTMG=0,
Disabled (Default); RBUSTMG=1, Enabled.
The BUSTMG pin (TQFP package only) is used to support this function. It is used to Enable/Disable the High Speed
CPU Read and Write function. It is defined as: BUSTMG = 0, the High Speed CPU Read and Write operations are
enabled; BUSTMG = 1, the High Speed CPU Read and Write operations are disabled if the RBUSTMG bit is 0. If
BUSTMG = 1 and RBUSTMG = 1, High Speed CPU Read operations are enabled (see definition of RBUSTMG bit
below).
SMSC COM20020I 3.3V Rev.E
Page 18
DATASHEET
Revision 09-11-06