COM20020I_0609 Datasheet, PDF (49/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
AD0-AD2,
D3-D7
nCS
ALE
nRD
VALID
t1
t2,
t4
t3
t9
t6
t5
VALID DATA
t10
t7
nWR
t13 _{Note 3}
t8
t11
t12
Note 2
PLCC Package: Must be RBUSTMG bit = 0,
TQFP Package: Must be ^MB^UU^SS^TTM^BEG^: p^Ri^Bn^U=^STH^MIG^GH^ba^itn⁼d⁰RBUSTMG bit =0
Parameter
t1 Address Setup to ALE Low
t2 Address Hold from ALE Low
t3 nCS Setup to ALE Low
t4 nCS Hold from ALE Low
t5 ALE Low to nRD Low
t6 nRD Low to Valid Data
t7 nRD High to Data High Impedance
t8 Cycle Time (nRD Low to Next Time Low)
t9 ALE High Width
t10 ALE Low Width
t11 nRD Low Width
t12 nRD High Width
t13 nWR to nRD Low
min
20
10
10
10
15
0
4TARB*
20
20
60
20
20
max units
nS
nS
nS
nS
nS
40
nS
20
nS
nS
nS
nS
nS
nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 2: _{Read cycle for Address Pointer Low/High Registers occurring after a read from}
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
Figure 12 - Multiplexed Bus, 80xx-Like Control Signals; Read Cycle
SMSC COM20020I 3.3V Rev.E
Page 49
DATASHEET
Revision 09-11-06