COM20020I_0609 Datasheet, PDF (35/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
BIT
BIT NAME
1,0 Reconfiguration
Timer 1, 0
SYMBOL
DESCRIPTION
RCNTM1,0
These bits are used to program the reconfiguration timer as a
function of maximum node count. These bits set the time out
period of the reconfiguration timer as shown below. The time
out periods shown are for 5 Mbps.
RCNTM1 RCNTM0 Time Out Period Max Node Count
0
0
420 mS
Up to 255 nodes
0
1
105 mS
Up to 64 nodes
1
0
52.5 mS
Up to 32 nodes
1
1
26.25 mS*
Up to 16 nodes
Note*: The node ID value 255 must exist in the network for
26.25 mS timeout to be valid.
D0-D7
Data Register
I/O Address 04H
Memory
Data Bus
8
Address Pointer Register
I/O Address 02H I/O Address 03H
High
Low
11-Bit Counter
Memory
Address Bus
11
2K x 8
INTERNAL
RAM
Figure 8 – Sequential Access Operation
6.3 Internal Ram
The integration of the 2K x 8 RAM in the COM20020I 3V represents significant real estate savings. The most obvious
benefit is the 48 pin package in which the device is now placed (a direct result of the integration of RAM). In addition, the
PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and control
functions which were necessary to interface to the RAM. The integration of RAM represents significant cost savings
because it isolates the system designer from the changing costs of external RAM and it minimizes reliability problems,
assembly time and costs, and layout complexity.
SMSC COM20020I 3.3V Rev.E
Page 35
DATASHEET
Revision 09-11-06