COM20020I_0609 Datasheet, PDF (51/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
AD0-AD2,
D3-D7
nCS
VALID
t1
t2,
t4
VALID DATA
ALE
nWR
nRD
t3
t9
t5
t13 ^{Note 3}
t10
t6
t11
t7
Note 2
t8**
t12
t8
PLCC Package: Don’t care RBUSTMG bit, TQFP Package: Must be BUSTMG pin = HIGH
Parameter
t1 Address Setup to ALE Low
t2 Address Hold from ALE Low
t3 nCS Setup to ALE Low
t4 nCS Hold from ALE Low
t5 ALE Low to nDS Low
t6 Valid Data Setup to nDS High
t7 Data Hold from nDS High
t8 Cycle Time (nWR to Next )**
t9 _{ALE High Width}
t10 ALE Low Width
t11 nWR Low Width
t12 nWR High Width
t13 nRD to nWR Low
min
20
10
10
10
15
30
10
4TARB*
20
20
20
20
20
max
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
** Note 2: _{Any cycle occurring after a write to Address Pointer Low Register requires a}
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: _{Write cycle for Address Pointer Low Register occurring after a read from Data}
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
Figure 14 - Multiplexed Bus, 80xx-Like Control Signals; Write Cycle
SMSC COM20020I 3.3V Rev.E
Page 51
DATASHEET
Revision 09-11-06