COM20020I_0609 Datasheet, PDF (62/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
4.0V
XTAL1
t1
t2
1.0V
t3
50% of VDD
Parameter
t1
Input Clock High Time
t2
Input Clock Low Time
t3
Input Clock Period*
t4
Input Clock Frequency*
t5
Frequency Accuracy*
min typ max units
20
nS
20
nS
50
100 ^nS
10
20 MHz
-200
200 ppm
Note*: Input clock frequency must be 20 MHz (+- 100ppm or better) to use the internal Clock Multiplier.
t4 and t5 are applied to crystal oscillaton.
Figure 25 – TTL Input Timing On XTAL1 Pin
t1
nRESET
nINTR
t2
Parameter
min typ
t1
nRESET Pulse Width***
t2
nINTR High to Next nINTR Low EF = 0
EF = 1
5TXTL^*
TDR**/2
4TXTL*
Note*: XTTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, T DR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after V DD was over 3V.
max units
Figure 26 – Reset And Interrupt Timing
SMSC COM20020I 3.3V Rev.E
Page 62
DATASHEET
Revision 09-11-06