COM20020I_0609 Datasheet, PDF (25/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
ADDR
00
01
02
03
04
05
06
07-0
07-1
07-2
07-3
07-4
MSB
RI/TR1
0
C7
RD-DA
TA
A7
C6
AUTO-
INC
A6
D7
D6
(R/W)* (R/W)*
RESE
T
TID7
NID7
P1-MO
DE
0
RBUS-
TMG
CCHEN
TID6
NID6
FOUR
NAKS
0
0
Table 3 - Write Register Summary
0
C5
0
A5
D5
0
TXEN
TID5
NID5
0
0
0
WRITE
0
EXCNAK
C4
C3
0
0
A4
A3
D4
D3
0
0
ET1
ET2
TID4
NID4
RCV-
ALL
0
CKUP
TID3
NID3
CKP3
0
EF
RECO
N
C2
A10
A2
D2
SUB-A
D2
BACK-
PLANE
TID2
NID2
CKP2
0
NO-
SYNC
NEW
NEXTID
C1
A9
A1
D1
SUB-
AD1
SUB-
AD1
TID1
NID1
CKP1
0
RCN-
TM1
LSB
TA/
TTA
C0
A8
A0
D0
SUB-
AD0
SUB-
AD0
TID0
NID0
SLOW-
ARB
0
RCN-
TM0
REGISTER
INTERRUPT
MASK
COMMAND
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA
SUBADR
CONFIG-
URATION
TENTID
NODEID
SETUP1
TEST
SETUP2
Note*:(R/W) These bits can be Written or Read. For more information see Appendix C.
6.2 INTERNAL REGISTERS
The COM20020I 3V contains 14 internal registers. Table 2 and Table 3 illustrate the COM20020I 3V register map. All
undefined bits are read as undefined and must be written as logic "0".
Interrupt Mask Register (IMR)
The COM20020I 3V is capable of generating an interrupt signal when certain status bits become true. A write to the IMR
specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position
as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic "1" in a particular position
enables the corresponding interrupt. The Status bits capable of generating an interrupt include the Receiver Inhibited bit,
New Next ID bit, Excessive NAK bit, Reconfiguration Timer bit, and Transmitter Available bit. No other Status or
Diagnostic Status bits can generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to produce the interrupt
signal. An RI or TA interrupt is masked when the corresponding mask bit is reset to logic "0", but will reappear when the
corresponding mask bit is set to logic "1" again, unless the interrupt status condition has been cleared by this time. A
RECON interrupt is cleared when the "Clear Flags" command is issued. An EXCNAK interrupt is cleared when the
"POR Clear Flags" command is issued. A New Next ID interrupt is cleared by reading the Next ID Register. The
Interrupt Mask Register defaults to the value 0000 0000 upon hardware reset.
Data Register
This read/write 8-bit register is used as the channel through which the data to and from the RAM passes. The data is
placed in or retrieved from the address location presently specified by the address pointer. The contents of the Data
Register are undefined upon hardware reset. In case of READ operation, the Data Register is loaded with the contents
of COM20020I 3V Internal Memory upon writing Address Pointer low only once.
Tentative ID Register
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly
(please refer to the Configuration Register and SUB ADR Register). The Tentative ID Register can be used while the
node is on-line to build a network map of those nodes existing on the network. It minimizes the need for operator
SMSC COM20020I 3.3V Rev.E
Page 25
DATASHEET
Revision 09-11-06