COM20020I_0609 Datasheet, PDF (30/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
DATA
0000 0000
0000 0001
0000 0010
b0fn n100
00fn n011
0000 c101
000r p110
0000 1000
0001 1000
COMMAND
Clear
Transmit
Interrupt
Disable
Transmitter
Disable
Receiver
Enable
Receive to
Page fnn
Enable
Transmit from
Page fnn
Define
Configuration
Clear Flags
Clear
Receive
Interrupt
Start Internal
Operation
Table 6 - COMMAND REGISTER
DESCRIPTION
This command is used only in the Command Chaining operation.
Please refer to the Command Chaining section for definition of this
command.
This command will cancel any pending transmit command
(transmission that has not yet started) and will set the TA
(Transmitter Available) status bit to logic "1" when the COM20020I
3V next receives the token.
This command will cancel any pending receive command. If the
COM20020I 3V is not yet receiving a packet, the RI (Receiver
Inhibited) bit will be set to logic "1" the next time the token is
received. If packet reception is already underway, reception will
run to its normal conclusion.
This command allows the COM20020I 3V to receive data packets
into RAM buffer page fnn and resets the RI status bit to logic "0".
The values placed in the "nn" bits indicate the page that the data
will be received into (page 0, 1, 2, or 3). If the value of "f" is a
logic "1", an offset of 256 bytes will be added to that page
specified in "nn", allowing a finer resolution of the buffer. Refer to
the Selecting RAM Page Size section for further detail. If the
value of "b" is logic "1", the device will also receive broadcasts
(transmissions to ID zero). The RI status bit is set to logic "1"
upon successful reception of a message.
This command prepares the COM20020I 3V to begin a transmit
sequence from RAM buffer page fnn the next time it receives the
token. The values of the "nn" bits indicate which page to transmit
from (0, 1, 2, or 3). If "f" is logic "1", an offset of 256 bytes is the
start of the page specified in "nn", allowing a finer resolution of the
buffer. Refer to the Selecting RAM Page Size section for further
detail. When this command is loaded, the TA and TMA bits are
reset to logic "0". The TA bit is set to logic "1" upon completion of
the transmit sequence. The TMA bit will have been set by this
time if the device has received an ACK from the destination node.
The ACK is strictly hardware level, sent by the receiving node
before its microcontroller is even aware of message reception.
Refer to Figure 1 for details of the transmit sequence and its
relation to the TA and TMA status bits.
This command defines the maximum length of packets that may
be handled by the device. If "c" is a logic "1", the device handles
both long and short packets. If "c" is a logic "0", the device
handles only short packets.
This command resets certain status bits of the COM20020I 3V. A
logic "1" on "p" resets the POR status bit and the EXCNAK
Diagnostic status bit. A logic "1" on "r" resets the RECON status
bit.
This command is used only in the Command Chaining operation.
Please refer to the Command Chaining section for definition of this
command.
This command restarts the stopped internal operation after
changing CKUP bit.
Table 7 - Address Pointer High Register
SMSC COM20020I 3.3V Rev.E
Page 30
DATASHEET
Revision 09-11-06