COM20020I_0609 Datasheet, PDF (53/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
A0-A2
VALID
t1
t2
nCS
nRD
nWR
t3
Note 3
t10
t6
t5
t8
t4
t9
Note 2
t7
D0-D7
VALID DATA
CASE 2 PLCC Package: Must be RBUSTMG bit = 1,
TQFP Package:CMAuSsEt b2e: BRUBSUTSMTGMGpinbit==L1OW or RBUSTMG bit =1
Parameter
t1 Address Setup to nRD Active
t2 ^{Address Hold from nRD Inactive}
t3 nCS Setup to nRD Active
t4 ^{nCS Hold from nRD Inactive}
t5 ^{Cycle Time (nRD Low to Next Time Low)}
t6 nRD Low to Valid Data
t7 nRD High to Data High Impedance
t8 nRD Low Width
t9 nRD High Width
t10 nWR to nRD Low
min
max
-5
0
-5
0
4TARB*+30
60**
0
20
100
30
20
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
** t6 is measured from the latest active (valid) timing among nCS, nRD, A0-A2.
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 2: _{Read cycle for Address Pointer Low/High Registers occurring after a read from}
Note 3:
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
Figure 16 - Non-Multiplexed Bus, 80xx-Like Control Signals; Read Cycle
SMSC COM20020I 3.3V Rev.E
Page 53
DATASHEET
Revision 09-11-06