COM20020I_0609 Datasheet, PDF (31/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
BIT
BIT NAME
7 Read Data
6 Auto Increment
5-3 (Reserved)
2-0 Address 10-8
SYMBOL
RDDATA
AUTOINC
A10-A8
DESCRIPTION
This bit tells the COM20020I 3V whether the following
access will be a read or write. A logic "1" prepares the
device for a read, a logic "0" prepares it for a write.
This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic
increment of the pointer after each access, while a logic "0"
disables this function. Please refer to the Sequential
Access Memory section for further detail.
These bits are undefined. They must be 0.
These bits hold the upper three address bits which provide
addresses to RAM.
BIT
BIT NAME
7-0 Address 7-0
Table 8 - Address Pointer Low Register
SYMBOL
DESCRIPTION
A7-A0
These bits hold the lower 8 address bits which provide the
addresses to RAM.
BIT
BIT NAME
7-3 Reserved
2,1,0 Sub Address 2,1,0
Table 9
SYMBOL
SUBAD
2,1,0
- SUB ADDRESS REGISTER
DESCRIPTION
These bits are undefined. They must be 0.
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0 Register
0
0
0
Tentative ID (Same
0
0
1
Node ID
as in
0
1
0
Setup 1
Config
0
1
1
Next ID
Register)
1
0
0
Setup 2
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by
writing the Configuration Register.
BIT
BIT NAME
7 Reset
6 Command
Chaining Enable
Table 10 - Configuration Register
SYMBOL
DESCRIPTION
RESET
A software reset of the COM20020I 3V is executed by writing
a logic "1" to this bit. A software reset does not reset the
microcontroller interface mode, nor does it affect the
Configuration Register. The only registers that the software
reset affect are the Status Register, the Next ID Register, and
the Diagnostic Status Register. This bit must be brought
back to logic "0" to release the reset.
CCHEN
This bit, if high, enables the Command Chaining operation of
the device. Please refer to the Command Chaining section
for further details. A low level on this bit ensures software
compatibility with previous SMSC ARCNET devices.
SMSC COM20020I 3.3V Rev.E
Page 31
DATASHEET
Revision 09-11-06