COM20020I_0609 Datasheet, PDF (24/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Chapter 6 Functional Description
6.1 Microsequencer
The COM20020I 3V contains an internal microsequencer which performs all of the control operations necessary to
carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program counter, two instruction
registers, an instruction decoder, a no-op generator, jump logic, and reconfiguration logic.
The COM20020I 3V derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier. These clocks
provide the rate at which the instructions are executed within the COM20020I 3V. The 10 MHz clock is the rate at
which the program counter operates, while the 5 MHz clock is the rate at which the instructions are executed. The
microprogram is stored in the ROM and the instructions are fetched and then placed into the instruction registers.
One register holds the opcode, while the other holds the immediate data. Once the instruction is fetched, it is
decoded by the internal instruction decoder, at which point the COM20020I 3V proceeds to execute the instruction.
When a no-op instruction is encountered, the microsequencer enters a timed loop and the program counter is
temporarily stopped until the loop is complete. When a jump instruction is encountered, the program counter is loaded
with the jump address from the ROM. The COM20020I 3V contains an internal reconfiguration timer which interrupts
the microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of the
Diagnostic Status Register is set.
REGISTER
STATUS
DIAG.
STATUS
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA
SUB ADR
CONFIG-
URATION
TENTID
NODE ID
SETUP1
NEXT ID
SETUP2
MSB
RI/TRI
MY-RECON
RD-DATA
A7
D7
(R/W)*
RESET
TID7
NID7
P1 MODE
NXT ID7
RBUS-TMG
Table 2 - Read Register Summary
READ
X/RI X/TA POR TEST RECON
DUPID RCV- TOKEN EXC-N TENTID
ACT
AK
AUTO- X
X
INC
X
A10
A6
A5
A4
A3
A2
D6
D5
D4
(R/W)* X
X
CCHE
N
TID6
NID6
FOUR
NAKS
NXT
ID6
X
TXEN
TID5
NID5
X
NXT
ID5
X
ET1
TID4
NID4
RCV-
ALL
NXT
ID4
CKUP
D3
X
ET2
TID3
NID3
CKP3
D2
SUB-AD
2
BACK-P
LANE
TID2
NID2
CKP2
NXT
ID3
EF
NXT
ID2
NO-SYN
C
TMA
NEW
NEXT
ID
A9
LSB
TA/
TTA
X
A8
A1
A0
D1
SUB-
AD1
SUB-
AD1
TID1
NID1
CKP1
NXT
ID1
RCN-
TM1
D0
SUB-A
D0
SUB-A
D0
TID0
NID0
SLOW-
ARB
NXT
ID0
RCM-T
M2
ADDR
00
01
02
03
04
05
06
07-0
07-1
07-2
07-3
07-4
Note*: (R/W) These bits can be Written or Read. For more information see Appendix C.
SMSC COM20020I 3.3V Rev.E
Page 24
DATASHEET
Revision 09-11-06