COM20020I_0609 Datasheet, PDF (34/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Table 12 - SETUP 2 REGISTER
BIT
BIT NAME
SYMBOL
DESCRIPTION
7 Read Bus Timing RBUSTMG This bit is used to Disable/Enable the High Speed CPU
Select
Read function for High Speed CPU bus support.
RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable.
That is, if BUSTMG (pin 26: Only for TQFP package) = 1
and RBUSTMG = 1, High Speed CPU Read operations are
enabled.
It does not influence write operation. High speed CPU
Read operation is only for non-multiplexed bus.
6,5 Reserved
These bits are undefined. They must be 0.
4 Clock Multiplier
CKUP
Higher frequency clocks are generated from the 20 MHz
crystal through the selection of these two bits as shown.
This clock multiplier is powered-down on default. After
changing the CKUP bit, the ARCNET core operation is
stopped and the internal PLL in the clock multiplier is
awakened and it starts to generate the 40 MHz. The lock out
time of the internal PLL is 8μSec typically. After 1 mS it is
necessary to write command data '18H' to command
register for re-starting the ARCNET core operation.
CAUTION: Changing the CKUP bit must be one time or less
after releasing a hardware reset.
CKUP Clock Frequency (Data Rate)
0
20 MHz (Up to 2.5Mbps) Default
1
40 MHz (Up to 5Mbps)
Note: After changing the CKUP bit, it is necessary to write a
command data '18H' to the command register. Because
after changing the CKUP bits, the internal operation is
stopped temporarily. The writing of the command is to start
the operation.
These initializing steps are shown below.
1) Hardware reset (Power ON)
2) Change CKUP bit
3) Wait 1mSec (wait until stable oscillation)
4) Write command '18H' (start internal
operation)
5) Start initializing routine (Execute existing
software)
3 Enhanced
Functions
EF
This bit is used to enable the new enhanced functions in the
COM20020I 3V. EF = 0: Disable (Default), EF = 1: Enable. If
EF = 0, the timing and function is the same as in the
COM20020I, Revision B. See appendix “A”. EF bit must
be ‘1’ if the data rate is over 5Mbps.
EF bit should be ‘1’ for new design customers.
EF bit should be ‘0’ for replacement customers.
2 No Synchronous
NOSYNC
This bit is used to enable the SYNC command during
initialization. NOSYNC= 0, Enable (Default) The line must
be idle for the RAM initialization sequence to be written.
NOSYNC= 1, Disable:) The line does not have to be idle for
the RAM initialization sequence to be written. See appendix
“A”.
SMSC COM20020I 3.3V Rev.E
Page 34
DATASHEET
Revision 09-11-06