COM20020I_0609 Datasheet, PDF (59/69 Pages) SMSC Corporation – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
CASE 2 is supported for TQFP Package ONLY
A0-A2
VALID
t1
t2
nCS
t4
DIR
t3
nDS
D0-D7
t5
t7
t10
t8
t11
Note 2
t6**
t9
t6
VALID DATA
CASE 2 PLCC Package: Not supported, TQFP Package: Must be BUSTMG pin = LOW
Parameter
t1 Address Setup to nDS Active
t2 Address Hold from nDS Inactive
min
max units
105
nS
100
nS
t3 nCS Setup to nDS Active
t4 nCS Hold from nDS Inactive
50
nS
0
nS
t5 DIR Setup to nDS Active
10
nS
t6 Cycle Time (nDS to Next Time )**
4TA_ARR_BB*
nS
t7 DIR Hold from nDS Inactive
10
nS
t8 Valid Data Setup to nDS High
303*0**
nS
t9 Data Hold from nDS High
10
nS
t10 nDS Low Width
2605
nS
t11 nDS High Width
2³0
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
**Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nDS to the leading edge
of the next nDS.
Write cycle for Address Pointer Low Registers occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Figure 22 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle
SMSC COM20020I 3.3V Rev.E
Page 59
DATASHEET
Revision 09-11-06