SI5369 Datasheet, PDF(9/84 Page) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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SI5369 Datasheet, PDF (9/84 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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Si5369

Table 3. AC Specifications

(VDD = 1.8 Â± 5%, 2.5 Â±10%, or 3.3 V Â±10%, TA = â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Single-Ended Reference Clock Input Pin XA (XB with cap to GND)

Input Resistance

XARIN

RATE[1:0] = LM, MH,

kï

ac coupled

Input Voltage Swing

XAVPP

RATE[1:0] = LM, MH,

0.5

1.2

VPP

ac coupled

Differential Reference Clock Input Pins (XA/XB)

Input Voltage Swing

XA/XBVPP

RATE[1:0] = LM, MH

0.5

2.4

VPP

CKINn Input Pins

Input Frequency

Input Duty Cycle

(Minimum Pulse

Width)

CKNF

0.002

CKNDC

Whichever is smaller

(i.e., the 40% / 60%

limitation applies only

to high frequency

clocks)

710

MHz

Input Capacitance

CKNCIN

Input Rise/Fall Time

CKNTRF

20â80%

See Figure 2

CKOUTn Output Pins

(See ordering section for speed grade vs frequency limits)

Output Frequency

(Output not config-

ured for CMOS or

Disabled)

CKOF

N1 ï³ 6

N1 = 5

N1 = 4

0.002

945

MHz

970

1134

MHz

1.213

1.4

GHz

Maximum Output

CKOF

Frequency in CMOS

Format

Output Rise/Fall

(20â80 %) @

CKOTRF Output not configured for

CMOS or Disabled

622.08 MHz output

See Figure 2

212.5

MHz

230

350

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit

the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

to submit a technical support request regarding the lock time of your frequency plan.

Rev. 1.0

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