SI5369 Datasheet, PDF (7/84 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5369
Table 2. DC Characteristics (Continued)
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Drive Current
CKO_IO
ICMOS[1:0] = 11
—
7.5
(CMOS driving into
V_DD = 1.8 V
CKO_VOL for output low
or CKO_VOH for output
high. CKOUT+ and
ICMOS[1:0] = 10
—
5.5
V_DD = 1.8 V
CKOUT– shorted exter-
nally)
ICMOS[1:0] = 01
—
3.5
V_DD = 1.8 V
—
mA
—
mA
—
mA
ICMOS[1:0] = 00
—
1.75
—
mA
V_DD = 1.8 V
ICMOS[1:0] = 11
—
32
V_DD = 3.3 V
—
mA
ICMOS[1:0] = 10
—
24
V_DD = 3.3 V
—
mA
ICMOS[1:0] = 01
—
16
V_DD = 3.3 V
—
mA
ICMOS[1:0] = 00
—
8
V_DD = 3.3 V
—
mA
2-Level LVCMOS Input Pins
Input Voltage Low
V_IL
V_DD = 1.71 V
—
—
0.5
V
V_DD = 2.25 V
—
—
0.7
V
V_DD = 2.97 V
—
—
0.8
V
Input Voltage High
V_IH
V_DD = 1.89 V
1.4
—
—
V
V_DD = 2.25 V
1.8
—
—
V
V_DD = 3.63 V
2.5
—
—
V
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
Rev. 1.0
7