SI5369 Datasheet, PDF (11/84 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5369
Table 3. AC Specifications (Continued)
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Phase Change due to
t_TEMP
Max phase changes from
—
Temperature
–40 to +85 °C
Variation¹
PLL Performance
(fin = fout = 622.08 MHz; BW = 7 Hz; LVPECL, XAXB = 114.285 MHz)
Lock Time²
t_LOCKMP Start of ICAL to of LOL
—
Settle Time²
t_SETTLE
Start of ICAL to F_OUT
—
within 5 ppm of final value
Output Clock Phase
t_{P_STEP}
After clock switch
—
Change
f3  128 kHz
Closed Loop Jitter
Peaking
Jitter Tolerance
J_PK
J_TOL
—
Jitter Frequency Loop 5000/BW
Bandwidth
Phase Noise
fout = 622.08 MHz
100 Hz Offset
—
1 kHz Offset
—
Typ
300
0.8
4.2
200
0.05
—
–95
–110
Max
Unit
500
ps
1.0
s
5.0
s
—
ps
0.1
dB
—
ns pk-pk
—
dBc/Hz
—
dBc/Hz
CKO_PN
10 kHz Offset
100 kHz Offset
—
–117
—
dBc/Hz
—
–118
—
dBc/Hz
1 MHz Offset
—
–131
—
dBc/Hz
Spurious Noise
SP_SPUR
Max spur @ n x F3
—
–67
—
dBc
(n  1, n x F3 < 100 MHz)
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit
the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
to submit a technical support request regarding the lock time of your frequency plan.
Rev. 1.0
11