SI5369 Datasheet, PDF (27/84 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5369
Register 2.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
BWSEL_REG [3:0]
Type
R/W
R
R
R
R
Reset value = 0100 0010
Bit
Name
Function
7:4 BWSEL_REG [3:0] BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to
take effect.
3:0
Reserved
Register 3.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name CKSEL_REG [1:0]
DHOLD SQ_ICAL
Type
R/W
R/W
R/W
R
R
R
R
Reset value = 0000 0101
Bit
Name
Function
7:6 CKSEL_REG [1:0] CKSEL_REG.
If the device is operating in manual register-based clock selection mode
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input
clock will be the active input clock. If CKSEL_PIN = 1, the CKSEL[1:0] input pins
continue to control clock selection and CKSEL_REG is of no consequence.
00: CKIN_1 selected.
01: CKIN_2 selected.
10: CKIN_3 selected.
11: CKIN_4 selected.
5
DHOLD
DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic
clock selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of all
of the input clocks.
4
SQ_ICAL
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (dis-
abled) during an internal calibration. See Table 8.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
3:0
Reserved
Rev. 1.0
27