SI5369 Datasheet, PDF (30/84 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5369
Register 6.
Bit
D7
D6
Name
Type
R
R
Reset value = 0010 1100
D5
D4
D3
SFOUT4_REG [2:0]
R/W
D2
D1
D0
SFOUT3_REG [2:0]
R/W
Bit
Name
Function
7:6
Reserved
5:3 SFOUT4_REG [2:0] SFOUT4_REG [2:0].
Controls output signal format and disable for CKOUT4 output buffer. The LVPECL
and CMOS output formats draw more current than either LVDS or CML; however,
there are restrictions in the allowed output format pin settings so that the maxi-
mum power dissipation for the TQFP devices is limited when they are operated at
3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output
must be disabled. When there are five enabled outputs, there can be no more
than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0 SFOUT3_REG [2:0] SFOUT3_REG [2:0].
Controls output signal format and disable for CKOUT3 output buffer. The LVPECL
and CMOS output formats draw more current than either LVDS or CML; however,
there are restrictions in the allowed output format pin settings so that the maxi-
mum power dissipation for the TQFP devices is limited when they are operated at
3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output
must be disabled. When there are five enabled outputs, there can be no more
than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
30
Rev. 1.0