SI5369 Datasheet, PDF (5/84 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5369
Table 2. DC Characteristics
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Supply Current^1,6
Symbol
Test Condition
Min
Typ
I_DD
LVPECL Format
—
394
622.08 MHz Out
All CKOUTs Enabled
Max
Unit
435
mA
LVPECL Format
—
253
284
mA
622.08 MHz Out
1 CKOUT Enabled
CMOS Format
—
278
400
mA
19.44 MHz Out
All CKOUTs Enabled
CMOS Format
—
229
261
mA
19.44 MHz Out
1 CKOUT Enabled
Disable Mode
—
165
—
mA
CKINn Input Pins²
Input Common Mode
Voltage (Input Thresh-
old Voltage)
V_ICM
1.8 V ± 5%
2.5 V ± 10%
0.9
—
1.4
V
1
—
1.7
V
3.3 V ± 10%
1.1
—
1.95
V
Input Resistance
CKN_RIN
Single-ended
20
40
60
k
Single-Ended Input
V_ISE
f_CKIN < 212.5 MHz
0.2
—
Voltage Swing
See Figure 1.
(See Absolute Specs)
f_CKIN > 212.5 MHz
0.25
—
See Figure 1.
—
V_PP
—
V_PP
Differential Input
Voltage Swing
V_ID
f_CKIN < 212.5 MHz
0.2
—
See Figure 1.
(See Absolute Specs)
fCKIN > 212.5 MHz
0.25
—
See Figure 1.
—
V_PP
—
V_PP
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
Rev. 1.0
5