SI5369 Datasheet, PDF (6/84 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5369
Table 2. DC Characteristics (Continued)
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Clocks (CKOUTn)^3,5,6
Common Mode
CKO_VCM
LVPECL 100  load
line-to-line
Differential Output
Swing
CKO_VD
LVPECL 100  load
line-to-line
Single Ended Output
Swing
CKO_VSE
LVPECL 100  load
line-to-line
Differential Output Volt- CKO_VD
age
CML 100  load
line-to-line
Common Mode
Output Voltage
CKO_VCM
CML 100  load
line-to-line
Differential Output Volt- CKO_VD
LVDS
age
100  load line-to-line
Low Swing LVDS
100  load line-to-line
Common Mode
Output Voltage
CKO_VCM
LVDS 100 load
line-to-line
Differential
Output Resistance
Output Voltage Low
CKO_RD CML, LVPECL, LVDS
CKO_VOLLH
CMOS
V_DD –1.42
—
1.1
—
0.5
—
350
425
—
V_DD–0.36
500
700
350
425
1.125
1.2
—
200
—
—
V_DD –1.25
1.9
0.93
500
—
900
500
1.275
—
0.4
V
V_PP
V_PP
mV_PP
V
mV_PP
mV_PP
V

V
Output Voltage High
CKO_VOHLH
V_DD = 1.71 V
0.8 x V_DD
—
—
V
CMOS
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
6
Rev. 1.0