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SI5369 Datasheet, PDF (36/84 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Si5369
Register 19.
Bit
D7
Name FOS_EN
Type
R/W
D6
D5
FOS_THR [1:0]
R/W
D4
D3
VALTIME [1:0]
R/W
D2
D1
D0
LOCKT [2:0]
R/W
Reset value = 0010 1100
Bit
Name
Function
7
FOS_EN FOS_EN.
Frequency offset enable globally disables FOS. See the individual FOS enables (FOS-
x_EN, register 139).
00: FOS disable
01: FOS enabled by FOSx_EN
6:5 FOS_THR [1:0] FOS_THR [1:0].
Frequency Offset at which FOS is declared:
00: ± 11 to 12 ppm Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK.
01: ± 48 to 49 ppm (SMC).
10: ± 30 ppm SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK.
11: ± 200 ppm
4:3 VALTIME [1:0] VALTIME [1:0].
Sets amount of time for input clock to be valid before the associated alarm is removed.
00: 2 ms
01: 100 ms
10: 200 ms
11: 13 s
2:0 LOCKT [2:0] LOCKT [2:0].
Sets retrigger interval for one shot monitoring phase detector output. One shot is trig-
gered by phase slip in DSPLL. Refer to the Family Reference Manual for more details.
000: 106 ms
001: 53 ms
010: 26.5 ms
011: 13.3 ms
100: 6.6 ms
101: 3.3 ms
110: 1.66 ms
111: 833 µs
36
Rev. 1.0