SI5369 Datasheet, PDF (8/84 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5369
Table 2. DC Characteristics (Continued)
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
3-Level Input Pins⁴
Symbol
Test Condition
Input Voltage Low
V_ILL
Input Voltage Mid
V_IMM
Input Voltage High
V_IHH
Input Low Current
I_ILL
Input Mid Current
I_IMM
Input High Current
I_IHH
LVCMOS Output Pins
See Note 4
See Note 4
See Note 4
Min
—
0.45 x
V_DD
0.85 x
V_DD
–20
–2
—
Typ
Max
Unit
—
0.15 x V_DD
V
—
0.55 x V_DD
V
—
—
V
—
—
µA
—
+2
µA
—
20
µA
Output Voltage Low
V_OL
IO = 2 mA
V_DD = 1.71 V
—
—
0.4
V
Output Voltage Low
IO = 2 mA
V_DD = 2.97 V
—
—
0.4
V
Output Voltage High
V_OH
IO = –2 mA
V_DD –0.4
—
—
V
V_DD = 1.71 V
Output Voltage High
IO = –2 mA
V_DD –0.4
—
—
V
V_DD = 2.97 V
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
8
Rev. 1.0