SI53307 Datasheet, PDF (9/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
Table 11. Additive Jitter, Differential Clock Input
V_DD
Input^1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)³
Freq Clock Format Amplitude
Differential Clock Format
Typ
Max
(MHz)
V_IN
(Single-Ended,
Peak-to-Peak)
20%–80%
Slew Rate (V/
ns)
3.3
725
Differential
0.15
0.637
LVPECL
45
65
3.3
725
Differential
0.15
0.637
LVDS
50
65
3.3 156.25 Differential
0.5
0.458
LVPECL
160
185
3.3 156.25 Differential
0.5
0.458
LVDS
150
200
2.5
725
Differential
0.15
0.637
LVPECL
45
65
2.5
725
Differential
0.15
0.637
LVDS
50
65
2.5 156.25 Differential
0.5
0.458
LVPECL
145
185
2.5 156.25 Differential
0.5
0.458
LVDS
145
195
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See application note, “AN766: Understanding and
Optimizing Clock Buffer’s Additive Jitter Performance” for more information.
2. AC-coupled differential inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
Rev. 1.0
9