SI53307 Datasheet, PDF (12/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
2. Functional Description
The Si53307 is a low jitter, low skew 2:2 differential buffer with an integrated 2:1 input clock mux. The device has a
universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select
the active input clock. The Si53307 features control pins for synchronous output enable, output signal format
selection and LVCMOS drive strength.
2.1. Universal, Any-Format Input
The Si53307 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including
LVPECL, low-power LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various ac- and
dc-coupling options supported by the device. Figures 2, 3, and 4 show the recommended input clock termination
options. For the best high-speed performance, the use of differential formats is recommended. For both single-
ended and differential input clocks, the fastest possible slew rate is recommended since low slew rates can
increase the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is
recommended for differential formats and 1.0 V/ns for single-ended formats. For more information, see application
note, “AN766: Understanding and Optimizing Clock Buffer Additive Jitter Performance”.
Table 15. LVPECL, LVCMOS, and LVDS
1.8 V
2.5/3.3 V
LVPECL
AC-Couple DC-Couple
N/A
N/A
Yes
Yes
LVCMOS
AC-Couple DC-Couple
No
No
No
Yes
LVDS
AC-Couple DC-Couple
Yes
No
Yes
Yes
1.8 V
2.5/3.3 V
Table 16. HCSL and CML
HCSL
AC-Couple DC-Couple
No
No
Yes (3.3 V) Yes (3.3 V)
CML
AC-Couple DC-Couple
Yes
No
Yes
No
0.1 µF
CLKx
Si533xx
100 
/CLKx
0.1 µF
Figure 2. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-coupled Input
Termination
VDDO_{= 3.3 V or 2.5 V}
CMOS
Driver
Rs
50
V_DD
1 k
CLKx
/CLKx
V_DD
Si533xx
1 k ^VTERM ^{= V}DD^/2
Figure 3. LVCMOS DC-coupled Input Termination
12
Rev. 1.0